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Technical Paper Round-up: June 14


New technical papers added to Semiconductor Engineering’s library this week. [table id=33 /] Semiconductor Engineering is in the process of building this library of research papers. Please send suggestions (via comments section below) for what else you’d like us to incorporate. If you have research papers you are trying to promote, we will review them to see if they are a good fit f... » read more

Cu/SiO₂ Hybrid Bond Interconnects


Technical paper titled "Microstructure Development of Cu/SiO₂ Hybrid Bond Interconnects After Reliability Tests" from researchers at TU Dresden and others. Abstract: "The focus of this study is a detailed characterization of hybrid Cu/SiO 2 wafer-to-wafer bonding interconnects after reliability testing. Hybrid bonding (or direct bond interconnect) is a technology of choice for fine pitch... » read more

Next Steps For Panel-Level Packaging


Tanja Braun, group manager at Fraunhofer Institute for Reliability and Microintegration (IZM), sat down with Semiconductor Engineering to talk about III-V device packaging, chiplets, fan-out and panel-level processing. Fraunhofer IZM recently announced a new phase of its panel-level packaging consortium. What follows are excerpts of that discussion. SE: IC packaging isn’t new, but years a... » read more

Fan-Out Packaging Options Grow


Chipmakers, OSATs and R&D organizations are developing the next wave of fan-out packages for a range of applications, but sorting out the new options and finding the right solution is proving to be a challenge. Fan-out is a way to assemble one or more dies in an advanced package, enabling chips with better performance and more I/Os for applications like computing, IoT, networking and sma... » read more