Fan-Out Panel-Level Packaging Hurdles

The economics look attractive, but first the industry needs convergence on panel size, process tools, and materials.


Fan-out panel-level packaging (FOPLP) promises to significantly lower assembly costs over fan-out wafer-level packaging, providing the relevant processes for die placement, molding and redistribution layers (RDLs) formation can be scaled up with equivalent yield.

There is still much work to be done before that happens. Until now, FOPLP has been adopted for devices that are manufactured in very high volumes, such as power management ICs for mobile phones, using relatively relaxed RDL dimensions. In addition, the industry has yet to settle on a standard panel size and establish assembly design kits to ensure design-to-manufacturing compliance.

There are several main challenges facing OSATs and their engineering teams:

  • Changing over the assembly line equipment from a 300mm round form factor to rectangular form factors as large as a 650 x 650mm requires a substantial investment.
  • Current production processes typically use looser RDL pitches and low layer counts for consumer and wearable industry products. More aggressive panel process nodes for FOPLP processes are still in the pilot production stage.
  • Significant process development needs to occur. To make the transition will require addressing the technology process step and material challenges that come with the immensely greater area of a panel.

“We expect to see a significant increase in adoption of FOPLP beyond mobile/wearable applications,” said Monita Pau, strategic marketing director for advanced packaging at Onto Innovation. “There are also a growing number of packaging houses providing FOPLP capabilities.”

The upside for growth in this market is significant. “Looking at the total fan-out packaging market, FOWLP is still the mainstream carrier type, and FOPLP is still considered a niche market, said Gabriela Pereira, semiconductor packaging analyst for Yole Group. “In terms of revenue, Yole Intelligence, in the Fan-out Packaging 2023 report, estimates the FOPLP market was approximately $41 million in 2022[1], and it is expected to show a significant CAGR of 32.5% in the next five years, growing to $221 million in 2028. In fact, FOPLP adoption will grow faster than the overall fan-out market, and its market share, vis-à-vis FOWLP, will move from 2% in 2022 to 8% in 2028. This means that FOPLP is expected to grow in the coming years as more panel lines become available and higher yields provide better cost efficiency.”

That level of cost efficiency is significant. The relative cost savings associated with panels versus round wafers can exceed 20% (see figure 1).

Fig. 1: Projected cost savings for wafer vs. panels, by package size. Source: Yole Intelligence

In terms of process capability, FOPLP can be viewed as a technology that straddles fan-out wafer level packaging (FOWLP) and printed circuit board processing. Over the last 10 years, engineering teams at major assembly companies and research institutes have developed panel-level packaging, in some cases by leveraging existing processes and tools.

“FOPLP has been adopted by a number of companies over the last five to seven years, but has faced a number of challenges when it comes to adoption, even at the lower technology requirements such as 10/10 µm line/space for power management devices,” said Mark Gerber, senior direct of engineering and technical marketing at ASE. “Factors such as package body size, line/space requirements, and volume requirements to fill the line have limited the wide adoption. Challenges with these factors will continue to drive new innovations for finer line/space requirements (yield considerations) and a higher number of RDL layers, while managing warpage across the larger panel. ASE has developed panel-level over the last seven-plus years, and continues to refine capabilities in support of next generation applications.”

Process steps
Fundamentally, fan-out wafer and panel-level packaging have similar process flows for chip-first or chip-last assembly (see figure 2). There are pros and cons to both approaches. For instance, with chip last engineers can perform electric test and inspection to ensure only known-good die placement on the RDL. With the chip first approach, an adaptive process can mitigate die shift on the RDL substrate.

“Currently, FOPLP production mainly involves chip-first approaches, with both face-down and face-up options available, and usually targets simpler, smaller packages,” said Yole’s Pereira. “Face-down processes connect RDL/UBM layers directly on solder bumps, while face-up processes use copper pillar bumps as a first layer of interconnection from the RDL/UBM, allowing smaller I/O pitches. Several players also are developing chip-last solutions targeting large multi-die systems-in-package (SiPs) for high-density applications with finer lines and spaces, reduced bump pitches, and more RDL layers. Chip-last is the preferred alternative to build fan-out RDL interposers, which are emerging and gaining industry attention to package high-performance devices (CPU, GPU, FPGA, etc.) as a less-costly solution than silicon interposers.”

Fig. 2: Chip-first vs. chip-last fan-out assembly processes for wafer or panel. Source: TechSearch International

For semiconductor providers, the tipping points for moving from wafer-level fan-out to panel-level fan-out depend on risk and cost. For the latter, FOPLP needs to create units with yield on par with FOWLP at a significantly lower cost. “Wafer fan-out technology came earlier than panel,” said Daniel Fann, marketing director at PowerTech Technology Inc. “It becomes a challenge to convince our customers to evaluate panel fan-out unless there is an immediate urgency. Also, we need to prove panel fan-out has similar production yield to wafer fan-out.”

Process technology roadmap barriers
Panel-level package processes have been approached by adapting either wafer-level package technology or PCB technology for processing over large rectangular format sizes. Each process technology has given materials to work with, which must overcome the challenges when creating substrate/assembled structures with different materials. Differences in coefficients of thermal expansion (CTEs) [2] affect the assembled product as it runs through the various processing steps at different temperatures.

Fig. 3: Process flows comparing wafer- and PCB-based technologies. Source: Fraunhofer Institute for Reliability and Microintegration IZM

Improving yield requires breaking through technological challenges. In general, engineering teams working on FOPLP face the same challenges as those working on FOWPLP — warpage, lithography uniformity, and die shift. But those challenges are amplified fivefold when going from a 300mm wafer (70,807 square mm) to a 600 x 600mm panel (360,000 square mm).

“Generally, FOPLP is using square or rectangular support panels, so any spin on technology needs to be replaced by lamination or spray coating,” said Doug Scott, senior vice president of Amkor’s Wafer Services Business Unit. “Process uniformity of metal dep, plating, and etch will need to be consistent over a non-round, large panel format versus a proven, round 300mm format. Panel pre-processing and post-processing also will need to be defined, depending on how and what process steps the FOPLP processing is using.”

As RDL line width and spacing decreases from line/space of 9/12µm to 5/5µm, and eventually 2/2 µm, and correspondingly bump/pad/pillar density increases, the number of challenges for FOPLP interconnect processes increase. Multiple experts noted that engineering teams can address these challenges by identifying the right mix of materials for mold compounds, temporary carrier, adhesives, interconnect, and substrate. The optimal mix can differ by process flow.

“If you dig into the various fan-out process flows you will find for each process challenges and potential for optimization. Of course, some approaches are further developed than others,” said Tanja Braun, deputy group manager at the Fraunhofer Institute for Reliability and Microintegration IZM. “We see trends for fine lines and spaces, multiple chips, and larger chips. These further drive the technology development. In particular, we see a lot of new materials, there are technical challenges to resolve. There is not one best process flow. If you use the chip face-up approach, you do preparations with copper plating. In addition, you need to carefully consider the different chip heights because it has an impact.”

This is easy when the whole manufacturing process is done in one factory, but this approach becomes more complicated when sourcing chips from different suppliers. “When you have a RDL first approach you can use film technology, which provides fine line width and the layer structuring,” said Braun. “This is also not so easy to do.”

Die shift, warpage and lithography
The FOPLP assembly process requires a multi-step process with carefully chosen temperatures. The CTE mismatch can range from a 3X to 5X difference. Consequently, the heating up and cooling down of the panel during the assembly process becomes a key variable that impacts warpage, material shrinkage and die shift.

Fig. 4: Process flow for carrier, epoxy molding. debonding and illustration of how CTE values need to be managed for the changes in temperature during process flow. Source: Fraunhofer Institute for Reliability and Microintegration IZM


Fig. 5: How warpage changes with substrate size. Source: Fraunhofer Institute for Reliability and Microintegration IZMFig. 5: How warpage changes with substrate size. Source: Fraunhofer Institute for Reliability and Microintegration IZM

All fan-out packaging requires temporary bonding of chips on a reconstituted substrate, which is later released. “The temporary bonding materials used depend on the carrier material and debonding process,” said Yole’s Pereira. “The most common debonding processes for FOPLP are laser debonding and thermal debonding, in which various types of adhesive layers, typically composed of thermoplastic or thermoset polymers, can be applied by spin-coating or lamination processes.”

In addition, the choice of temporary adhesives affects die shift. “To address die shift, we have developed a temporary die attach material that allows for extremely low shift during the molding process or the thermal compression bonding process later,” said Rama Puligadda, CTO of Brewer Science. “This is basically a material that goes on top of a holding substrate (i.e. temporary carrier). Next step is placing dies on this substrate, which is followed by molding or other bonding on top of the die. The technical goal is very little shift after or during these steps.”

Fig. 6: Warpage impacts die shift and bonding results. Die shift can be minimized using a warpage compensation tool. Source: Fraunhofer Institute for Reliability and Microintegration IZM

As copper line/spacing sizes decrease and the RDL layer counts increase the lithography challenges rise. Along with this is the panel uniformity challenge of build-up or thin film processes with material deposition.

“In the next three to five years, it looks like there will be a change in the processing of panels and substrates,” said Keith Best, director of product marketing for lithography at Onto Innovation. “Currently, substrates are made out of copper clad laminate (CCL). It’s cheap, a bit like PCB boards. But the problem with this material is it is not very stable. When you heat it to cure the dielectric layers, it changes shape. As that happens, all the RDL interconnect layers struggle to match up properly and layer-to-layer overlay becomes a challenge. One of the most challenging processing steps is lithography, because of overlay and CD control. Also, the plating step is really challenging because of controlling the RDL height and CD uniformity.”

Equipment vendors with decades of wafer fabrication experience are addressing these challenges. “The use of RDLs in panel-level packaging requires a high degree of uniformity in the panel, from electroplating to lithography,” said CheePing Lee, senior technical director at Lam Research. “Full panel uniformity is difficult due to size, shape, and warpage of the panel, and if not achieved may lead to topography issues on subsequent layers. Electroplating across a large panel uniformly is one of the most challenging process steps.”

He noted that Lam continues to develop specialized electroplating reactor technology to deliver uniform plating.

Enablers to lower cost
Both equipment investments and defining an assembly design kit file would have a positive impact on yield for panel fan-out technology. The transition to new equipment, materials and process recipes necessitates both empirical and simulation experimentation to fine-tune a production process.

“Due to the start-up investment costs needed, simulations are used to understand potential warpage, thermal, and mechanical concerns,” said Amkor’s Scott. “Amkor has a pilot production line at 650mm x 650mm, so we can also run optimization in parallel to simulation work. Changeover is expensive on a FOPLP line, so many experiments are validated on a 300mm line first before moving to the FOPLP line.”

Multi-physics simulation enables engineers to comprehend the intersection requirements that material choices, temperatures, and RDL dimensions have on the resulting requirements of low warpage, minimal die shift, and RDL pitches.

“Panel size is larger than a 12-inch wafer and thermal warpage control is the key,” said PTI’s Fann. “It could be optimized by selecting suitable carrier glass CTE, adjusting structure thickness, and select mold materials for balancing. Usually, a CAE tool to simulate warpage performance is needed. We use ANSYS-ME. To empirically measure warpage performance, we use Shadow Moire techniques.” [3, 4]

The key steps in creating RDL interconnects — lithography, etch, plating — also benefit from multi-physics simulation, which can be complemented with the building of predictive models based upon DOEs on a production line.

“SEMulator3D performs predictive modeling of etch, deposition, and other integrated processes, and can also model the effect of material options on device performance to identify problems prior to fabrication,” said Joseph Ervin, senior director for Semiverse Solutions at Lam Research. “It enables engineers to understand manufacturing effects early in the development process and reduce time-consuming and costly silicon learning cycles.”

RDL engineers who design advanced packages could benefit from adopting such simulation tools. In wafer fabrication, designers use process design kits (PDKs) in EDA tools to automate the complex routing to meet manufacturing design rules. Currently, the industry does not have  the equivalent for assembly, which would be assembly design kits (ADKs). Instead, designers and their tools use an assembly manufacturer’s data sheet. An ADK would provide a finer granularity of process information to consistently communicate the bounding boxes that dictate design manufacturability.

“ADKs have been talked about for the last 15 years,” said Kenneth Larsen, director, 3D IC product management, EDA Group at Synopsys. “They’re not there yet. And that’s a bit disappointing, because advanced packages are getting so complex in terms of number of connections. To drive automation like you do in the IC world, designers and their tools need manufacturing rules to obey. And to automate you need a starting point, an ADK.”

To ease the transition from their existing processes, assembly houses want to leverage existing equipment. In the short term, this approach saves investment cost. However it impedes equipment vendors from developing panel-specific tooling due to existing process flows, diverse panel sizes, and changes to process materials, temporary carriers/adhesives and trays.

Consider something as simple as the pick-and-place machines. “As you go to these heterogeneous integration devices, you’re placing multiple die types on the panel or the substrate, and panel is a great segment for multi-die circuit assembly,” said Glenn Farris, vice president of global customer operations and corporate marketing at Universal Instruments. “When you go to multi-die applications for panel fan-out, what do you do to get efficient assembly? Because of the accuracy requirements and decreased yield, people do not want to use multiple pick-and-place machines. Also, you have an unbalanced line. For example, you might have four of die A and two of die B. To address these concerns, we developed a machine that efficiently moves pre-scratched wafers in and out of a wafer table. It can do this with very little transition time from one die type to another die type.”

Fig.7: Multiple pick and place vs. single pick and place. Source: Universal Instruments Corp.

Chiplet-based designs for high-performance computing and ML specific products is where everyone hopes the cost benefits of panels will pay off. But factories are still learning how to improve yield on panels, which takes time. In the interim, the industry needs convergence on panel size, materials, and processes to ultimately drive yield up and costs down.

FOPLP offers semiconductor providers a platform to create fully heterogeneous products, combining die from different fabs or foundries. The tipping point from wafer substrates to panel substrates will occur when volume, yield and cost align. Investments in manufacturing standards and equipment need to be made ahead of time.

“FOPLP scaling timeline comes down to need — the need for lower costs with higher reliability, and the need for lower costs on very large package sizes,” said Amkor’s Scott. “Once volume applications push the need for capacity and costs not offered by existing 300mm formats, we will see much more adoption. Currently, various foundries/OSATs have made investments, but few are transitioning fully from 300mm to large panels. Amkor is positioned and working aggressively with its customers on FOPLP scaling timelines.”

— Liz Allan contributed to this story.



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