tag: OSATs

TSV Complexity Leads To Manufacturing Bottleneck
By Laura Peters - 22 Apr, 2026 - Comments: 1

Key Takeaways: Through-silicon vias are the biggest enabler of 3D chip stacking and chip-to-PCB connections through silicon interposers. The AI boom is causing HBM and advanced assembly shortages, straining the supply chain. Optimization around etch, fill and reveal help reduce TSV cost. Through-silicon vias (TSVs) provide essential interconnects between DRAM dies inside hig... » read more

AI Accelerators Usher In New Era For IC Test
By Laura Peters - 07 Apr, 2026 - Comments: 0

Key Takeaways The parallelism in AI accelerators enables low latency but complicates failure isolation. HBM can account for 50% of package cost, so known-good stack assurance is critical. DFT and test cooperate to solve final test, singulated die test, SLT, and in-system test for data centers. AI accelerators are used for everything from training large language models to mak... » read more

HBM4 Sticks With Microbumps, Postponing Hybrid Bonding
By Bryon Moyer - 13 Jan, 2026 - Comments: 0

The next generation of high-bandwidth memory, HBM4, was widely expected to require hybrid bonding to unlock a 16-high memory stack. A JEDEC move made that unnecessary with this generation, but it’s merely a postponement, not a cancellation. HBM has been in high demand for AI in data centers — especially for training. Data movement dominates energy consumption, and high-bandwidth memories... » read more

Rethinking Security In Semiconductor Testing: Why Containment Is The New Imperative
By Arik Peltz - 14 Oct, 2025 - Comments: 0

It’s nearly impossible to keep up with the headlines without stumbling upon another major cybersecurity incident. According to recent reports, 2024 witnessed a staggering 5.5 billion breaches globally. In the United States alone, the average cost of a single data breach clocked in at $9.36 million—slightly lower than 2023’s figure, but still a significant hit for any organization. On a gl... » read more

Infusing Trust Into The Supply Chain
By Anne Meixner - 09 Sep, 2025 - Comments: 0

An expanding supply chain of dies feeding multi-die products is prompting chipmakers to reassess and expand on ways to instill trust from end to end. This reaches deeper than just connecting disparate data. It requires integrating complex systems across vendors and protecting vendor data while instilling confidence in their customers and partners. Yet despite the time and effort that has bee... » read more

Detecting Slips, Scratches, Cracks In Wafers And Dies Becoming Harder
By Anne Meixner - 10 Jul, 2025 - Comments: 0

Defect detection requirements on the order of 10 defective parts per million (DPPM) are driving improvements in inspection tools’ resolution and throughput at foundries and OSATs. However, defects that manifest as slips, scratches, and micro-cracks continue to bedevil the prevalent optical inspection methods. These defects can range in size from nanometers to millimeters, some of which are... » read more

Who Is Most Likely To Link Financial And Manufacturing Data?
By Anne Meixner - 08 May, 2025 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to discuss which companies have the most to gain from linking financial data with manufacturing data analytics platforms with Dieter Rathei, CEO of DR Yield; Jon Holt, senior director of product management at PDF Solutions, Alex Burlak, vice president of advanced analytics and test at proteanTecs; and Dirk de Vries, technical program ma... » read more

Back-End Packaging And Test: From Lessons Learned To Future Innovations
By Jessica Albright - 20 Feb, 2025 - Comments: 0

The semiconductor industry is a hallmark of technological innovation, evolving rapidly to meet the demands of an increasingly digital world. At its core, semiconductor manufacturing involves two main stages: front-end processes, (wafer fabrication) and back-end processes (packaging and test). Wafer fabrication consists of creating microscopic electronic circuits on a silicon wafer. Packaging an... » read more

Advanced Packaging Evolution: Chiplet And Silicon Photonics-CPO
By Vincent Lin - 20 Feb, 2025 - Comments: 0

As we enter the AI era, the demand for enhanced connectivity in cloud services and AI computing continues to surge. With Moore’s Law slowing down, the increasing data rate requirements are surpassing the advancements of any single semiconductor technology. This shift underscores the importance of heterogeneous integration (HI) as a crucial solution for alleviating bandwidth bottlenecks. Tod... » read more

Assembly Design Rules Slowly Emerge
By Bryon Moyer - 27 Jan, 2025 - Comments: 0

Process design kits (PDKs) play an essential in ensuring that silicon technology can proceed from one generation to the next in a manner that design tools can keep up with. No such infrastructure has been needed for packaging in the past, but that's beginning to change with advanced packages. Heterogeneous assemblies are still ramping up, but their benefits are attracting new designs. “Chi... » read more

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