Many More Hurdles In Heterogeneous Integration

More resources will be needed for IC-to-package design, process extendibility, and improved reliability.


Advanced packaging options continue to stack up in the pursuit of “More than Moore” and higher levels of integration. It has become a place where many high-density interconnects converge, and where many new and familiar problems need to be addressed.

The industry’s first foray into fine-pitch multi-die packaging utilized silicon interposers with through-silicon vias (TSVs) to deliver substantial performance gains, though it is limited at high frequencies (4 to 6 GHz) and the cost of silicon interposers is high. This spurred the creation of alternatives such as high-density fan-out on bridges and substrates, each with its pros and cons.

To produce high-yielding modules with multiple chiplets, chipmakers are extending existing processes, making the most of fan-out and embedded configurations. They also are beginning to address the design challenges for advanced packaging, which call for the equivalent of a PDK for the assembly process.

“Chiplets and heterogenous integration have become the key enablers,” said Lihong Cao, senior director at ASE. “We see new breakthroughs happening in the market. There’s 2.5D silicon TSV integration for HPC, and there’s high-density fan-out RDL and bridge, and die-to-die connections using 3D microbumps and hybrid bonding for very high density.”

Interconnects are delving into the 2µm line-and-space regime for redistribution layers, and in advanced silicon interposers, 0.65µm to meet high-bandwidth requirements.

Co-design from EDA to package
The abundance of architectures and the high cost of failure in advanced packaging are encouraging closer collaboration between the device design processes and the packaging houses. EDA firms and OSATs are working on collaborative design toolsets to improve package performance, reduce cost, and shorten time-to-market for integrated packages.

Co-development seems essential to making chiplets in packages work, especially when it comes to combining chips from different companies. “One of our customers said it very well: “There are no 3D engineers being born. It’s all 2D engineers who overnight have to become 2.5D and 3D engineers,’“ said Shekhar Kapoor, senior director of product management at Synopsys. “In the SoC world there are methodologies, reference flows, and PDKs that have been developed over the years, and we’ve become used to them for doing the design. When you bring all these pieces together, you cannot look at it as a packaging guy’s problem or a silicon engineer’s problem. You have to start looking at it together.”

Others agree. “When we design chips, we do that based on a PDK we get from the foundry. The foundry invests in a process design kit, which gives us the data we need as ASIC designers to know what the technology is,” said John Park, product management group director in Cadence’s Custom IC & PCB Group. “We get the libraries, the sign-off design rules, and connectivity verification information. We know that whatever we’re creating, we’re going to be able to assemble that thing inside the foundry that provided the PDK because they’re guiding us. We don’t have that in packaging.”

That requires the various design, manufacturing, and packaging processes to be as automated as possible so engineers can focus on new designs and capabilities, not spending all their time on what today is more like a series of one-off packages with lots of individual components.

“The design tools are getting closer to comprehending this as a single design,” said Mike Kelly, vice president of chiplets/FCBGA integration at Amkor Technology. “We used to have a single chip, and you did all your timing and sign-off because you were inside of a single chip and everybody knew what was going on. With advanced packaging, you still have the timing considerations for which you need to be able to sign off when you’ve got multiple die. 3D adds another element, because in the physical world it’s easy for us to see a package as three-dimensional. But then, how do you abstract that into something you know is compatible with Verilog or IC design tools. I wouldn’t say it’s 100% ready, but big customers are making it work.”

Bringing a higher level of automation also will help speed quality and co-development time. “For the substrate design case, normally you have an APD file, which generates the Gerber file, and then you can route it,” said ASE’s Cao. “But how about the high-density RDL [redistribution layer] design?”

ASE’s RDL design flow uses three auto-routing steps. “We leverage the package design tool to optimize the RDL design,” she said. “After that, you generate the GDS file. Then, from the GDS file you do the LVS (layout versus schematic) check and the DRC (design rule check), and finally you will generate the mask using an automated mask design tool. Our approach can improve the layout cycle time by 50% by using the auto-route.”

Cao noted that the automask generator alone reduces process time from three days to about an hour.

Fig. 1: Using specifications from the device PDK, the packaging PDK flow include three auto-routing steps for the RDL that significantly speed development time. Source: ASE

But co-design of advanced packaging is best optimized within companies that perform their own chip and packages, such as TSMC, Intel, and UMC. Indeed, in-house developed chiplets and packages are the main advanced packages in high volume production.

1, 1,000, 1M interconnects
The number of electrical interconnections in a package is growing by leaps and bounds. With that come reliability issues.

“There are many, many more connections now, even in a modest 2.5D design, which easily contains 400,000 to 500,000 bumps,” said Marc Swinnen, director of  product marketing at Ansys. “Because these are microbumps, they cannot support a lot of shear stress. You’re putting 100 watts into some of these chips through these microbumps, but you don’t send it all through one microbump. You might have a 100 x 100 area of them, where they carry all the power in parallel. But if there’s some minor issue, like a bump void or a narrowing of the connection, once that gets hot the solder softens, and without adequate support the whole assembly starts warping and shifting from the differential thermal expansion. Reliability of that is a huge concern. Companies need to simulate mechanically the warping and flexing of these 3D assemblies under thermal and mechanical stresses, which has a direct impact on the reliability and expected lifespan in the field.”

To optimize package performance, device makers are focusing on optimizing die-to-die and die-to-package interconnects in various architectures, whether constructed vertically with microbumps, hybrid bonding, and bridges, or horizontally with fan-out redistribution layers. Deciding how and where interconnections will be formed is a becoming a big part of package integration.

“In advanced packaging, we need a very high-density interconnect fabric to bring all these things together — actually kind of fooling the system to think it’s still integrated on one chip, although there are multiple chips connected together,” said Eric Beyne, senior fellow, vice president for R&D, and program director for 3D system integration at imec. “A lot of effort is being spent today in trying to standardize the communication between chips, with HBM, BoW (Bunch of Wires), or UCIe. These standards are needed to provide guidelines on how technologies will go together between things like silicon interposers, silicon bridges, and high density RDL, because you need very, very high-density interconnects to make them work with low power consumption.”

For high-performance applications, high bandwidth between dies is essential. “If you’re doing a higher bandwidth interconnection between two dies, it tends to be a wide, low-power interface, so you need a fairly high-density interposer to make this happen,” said Mike Kelly, vice president of chiplets/FCBGA integration at Amkor Technology. “That’s probably the key difference for the packaging industry. You now require a really high-density integration scheme that allows you to connect dies so you don’t lose functional performance.”

In today’s advanced packages, thermal modeling helps characterize potential failure points, but this is not a new problem. “If you step back to the 10,000-foot level and look at electronic systems in general, the top two causes of failure are heat and interconnection failures,” said Ansys’ Swinnen. “They are related, of course. The heat often causes the interconnection failures. So interconnects have been a weak point in electronic designs from the get-go.”

Other weaknesses are more recent. “One failure mechanism that is coming up increasingly is low-k cracking,” said Kelly Morgan, senior principal application engineer for Sherlock at Ansys. “In this case, solder solidifies at a temperature of around 230°C, and the CTE mismatch between the low-k dielectric and solder creates a moment on the interconnect, which exercises tensile stress on the extra-low-k layer, causing a crack.”

Simulations of chemical and mechanical variability (see figure 1) are useful in early parts of the design process to prevent such problems.

Fig. 2: A structural simulation identifies subtle differences in z height, which plays a significant role in multi-die integration. Source: Ansys

Thermal and mechanical signatures should be considered during the initial design stages to best understand how the packaged system will perform, especially when stressed under fluctuating conditions of temperature, vibration or harsh environments. For instance, even though two die sitting side by side may be thermally exercised differently, their proximity to one another causes them to behave similarly.

“When we think about reliability in the packaging world, we’re always thinking about temperature cycles,” said Amkor’s Kelly. “You’ve got CTE differences, which create stresses as you’re cooling and heating. Normally the dies are as close together as we can get them, because you don’t want to make that interposer larger than it has to be because that’s a cost element. So the dies have a tough time not seeing the same thermal history.”

In semiconductors, the relative CTE mismatches between materials have always caused headaches when it comes to different material stacks. But with multiple packages on substrates, especially in non-symmetrical layouts, CTE mismatch is causing more serious problems.

The thermal expansion coefficient is an inverse function of stress temperature. The best CTE match is between silicon and silicon (hybrid bonding of wafers), or silicon-to-silicon interposer (SiO2/copper). CTE mismatches is large between silicon (2.5 ppm/K) and an organic interposer (BT, CTE = 15-16 ppm/K).

Because 90% of the heat from semiconductors rises, conductive thermal interface materials (TIMs) typically are sandwiched between the package and heat spreader to provide a good thermal path for heat transfer in the system. TIMs both dissipate heat and absorb some strain resulting from the mismatch of CTEs of the die, substrate and the integrated heat sink and heat spreader (lid) during temperature changes in assembly processing and field use.

There are several material solutions for TIMs including adhesives, gels, and greases. Most TIMs consist of a polymer base, such as an epoxy or silicone resin with conductive fillers such as aluminum, alumina, zinc oxide or silver. The advantage of these materials is high elongation and good workability. Unfortunately, thermal conductivity of these TIM materials is limited to around 10 W/m-K. Engineers are evaluating more conductive materials, such as gallium-indium and gallium-indium-tin alloys, as well as graphene to improve TIM technology. Even metal TIMs are being widely considered especially for high power applications.

Solder offers both challenges and solutions at advanced nodes. It is widely accepted that below a 10µm pitch, the industry must use hybrid bonding to connect copper-copper pads.

The industry roadmap shows a hybrid bonding approach, like Cu-to-Cu direct bonding at pitch under 10µm. Thermo-compression bonding (TCB) helps to achieve quality solder bonding with some warpage, although compression helps to overcome the intrinsic warpage. TCB with NCP/NCF (non-conductive paste/film) helps to address the challenges of large die/small pitch/capillary underfill or a pre-dispensed underfill.

One possible disadvantage is when the pitch is getting finer, the nature of forcing the solder in TCB between the copper tip and die pad can cause a protrusion from the solder, causing shorts.

Because changes in interconnect method are changing, as in the case of hybrid bonding, at the same time as advanced packaging is coming online, companies are joining together to solve manufacturing issues. For instance, UMC is partnering with Cadence, Winbond, Faraday, and ASE to develop a W2W (wafer-to-wafer) 3D-IC platform. By combining design, manufacturing, 3D-IC, test, and packaging expertise among suppliers, the group aims to adds 3D challenges, including design flows for vertical integration, alignment in wafer-to-wafer hybrid bonding, and a proven test and assembly path for 3D stacking. The project targets end-to-end solutions that include system-level verification.

Fan-out wafer-level packaging
Compared to established flip-chip packaging methods, fan-out packaging delivers superior electrical and thermal performance in a slightly smaller and thinner footprint. High density fan-out RDL comes in two flavors — chip first and chip last. The two are only slightly different, but each has its pros and cons.

In chip first, thermal release tape is applied to a carrier wafer, then the known good die (KGD) are picked and placed on the carrier. Next, overmolding is followed by carrier release, RDL formation, solder bumping, then singulation. In RDL first, the release layer again is deposited first, then the RDL. Known good die positioning comes next, followed by the overmold process, carrier release, solder ball deposition, and singulation.

Even though the chip last approach has the significant advantage from a yield standpoint, chip first is the more established approach.

So why do OSATs offer both processes? “The chip-first approach can offer slightly higher performance because the chip signal is directly connected to the RDL layer. But yield issues can drive specific decisions to use chip-last FOWLP,” said ASE’s Cao. “Currently the smallest microbump pitch is 55 to 40µm, and 35µm is in development. But with chip first you don’t need the microbump, so die-to-die pitch can be reduced to 25µm.”

Yield limits associated with microbump scaling encouraged the development of hybrid bonding processes that directly connect copper pads. But the high cost and complexity of hybrid bonding is encouraging R&D engineers to concentrate on manufacturing smaller bumps. Imec foresees a development path from today’s pitch limit of around 35µm to the 20µm level using a semi-additive copper microbump scheme with wafer-level underfill. For scaling below 10µm, a pad-to-bump connection is fabricated using tin bumps and Cu/Sn pads.

Fig. 3: A path to smaller microbumps fabrication. Source: imec

“If we go to smaller pitch connectivity, for instance, instead of going at 60µm pitch for bumps, we can go to 20µm pitch,” said imec’s Beyne. “That immediately reduces the length of that additional wiring and the area on the chips by a factor of three.”

The drive to higher-density interconnects for chiplet integrated packages is leading to more extendible approaches, including microbump scaling and hybrid bonding. But each package is essentially custom, which greatly increases the amount of engineering work required on the design side. As the industry gets more familiar with the options available between silicon and organic interposers, RDL fan-out, and embedded options, reliability — especially related to thermal and mechanical analysis — becomes a priority. Partnerships such as that among Cadence, UMC, Winbond, and ASE are likely to become more common as integration challenges now span design, manufacturing, testing and assembly. The industry will make chiplet integration in packaging a reality, even with chiplets from different device makers. But it is a question of when.

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