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Acoustic Metrology for Fine Pitch Microbumps in 3D IC


The continuing shift to 3D integration requires formation of electrical interconnects between multiple vertically stacked Si devices to enable high speed, high bandwidth connections. Microbumps and through silicon vias (TSVs) enable the high-density interconnects for die-to-die and die-to-wafer stacking for different applications. In this paper, we present acoustic metrology techniques for the ... » read more

Structural Integrity Of Chips


A new challenge is on the horizon, and it's one that could have some interesting consequences for chip design — structural integrity. Ever since the introduction of finFETs and 3D NAND, the lines have been blurring between electrical and mechanical engineering. After some initial reports of fins collapsing or breaking, and variable distances between layers, chipmakers figured out how to so... » read more

Designs Beyond The Reticle Limit


Designs continue to grow in size and complexity, but today they are reaching both physical and economic challenges. These challenges are causing a reversal of the integration trend that has provided much of the performance and power gains over the past couple of decades. The industry, far from giving up, is exploring new ways to enable designs to go beyond the reticle size, which is around 8... » read more

Ensuring HBM Reliability


Igor Elkanovich, CTO of GUC, and Evelyn Landman, CTO of proteanTecs, talk with Semiconductor Engineering about difficulties that crop up in advanced packaging, what’s redundant and what is not when using high-bandwidth memory, and how continuous in-circuit monitoring can identify potential problems before they happen. » read more

The Race To Next-Gen 2.5D/3D Packages


Several companies are racing each other to develop a new class of 2.5D and 3D packages based on various next-generation interconnect technologies. Intel, TSMC and others are exploring or developing future packages based on one emerging interconnect scheme, called copper-to-copper hybrid bonding. This technology provides a way to stack advanced dies using copper connections at the chip level,... » read more

Stacked Die Changes


Semiconductor Engineering sat down to discuss advanced packaging with David Pan, associate professor in the department of electrical and computer engineering at the University of Texas; Max Min, senior technical manager at Samsung; John Hunt, senior director of engineering at ASE; and Sitaram Arkalgud, vice president of 3D portfolio and technologies at Invensas. What follows are excerpts of tha... » read more

Tech Talk: 2.5D Issues


Bill Isaacson, director of ASIC marketing at eSilicon, about how viable this packaging approach is, organic vs. inorganic interposers, where the problems are, thermal coupling, interposer cost, and what will change over the next couple years. » read more