tag: hybrid bonding

How To Build Billions of Bumps
By Bryon Moyer - 18 Jun, 2026 - Comments: 0

Key Takeaways: Hybrid bonding can result in a package containing billions (and eventually trillions) of connections. Building that many connections successfully requires extreme process uniformity across a wafer. Inspection isn’t practical, and test benefits from internal test mechanisms. Hybrid bonding allows unprecedented signal pitch, but fully populating dies and inter... » read more

How to Create Efficient Bump and TSV Plans for Multi-Die Designs
By Synopsys - 18 Jun, 2026 - Comments: 0

In a multi-die design logical and physical interconnectivity between dies (or a die and interposer or other substrate) is achieved through microbumps or hybrid bonding pads between contacting dies. Today’s multi-die designs can have hundreds of thousands or millions of bumps, and this number will be increasing dramatically in the future, as hybrid bonding technology greatly reduces the pi... » read more

Making On-Chip Photonics Manufacturable
By Gregory Haley - 18 Jun, 2026 - Comments: 0

Key Takeaways: System-level energy and bandwidth pressures are pulling optics into the package faster than the manufacturing flow can mature. Photonics combines front-end fabrication, materials, thermal, cleanliness, and test into one problem that can’t be solved domain by domain. Test is moving upstream because discovering an optical failure after final assembly forfeits every goo... » read more

Re-Architecting Die-to-Die IO For AI
By Lakshmi Jain - 11 Jun, 2026 - Comments: 0

By Lakshmi Jain and Wei-Yu Ma As AI-driven workloads continue to push the boundaries of compute scale, power efficiency, and bandwidth density, conventional die-to-die interconnect technologies—such as SerDes-based links and wide parallel IO—are increasingly becoming limiting factors. These approaches struggle to meet the growing demands for higher bandwidth density and improved energy e... » read more

Advancing Heterogeneous Integration Through Industry Roadmap Improvements
By Ravi V. Mahajan - 21 May, 2026 - Comments: 0

Heterogeneous integration requires comprehensive roadmaps to support collaboration across the design and manufacturing of the next generation of semiconductor products and the systems they support. A global team of researchers from a broad spectrum of industry, academia, and research institutes led by Intel has published a perspective in the March 2026 issue of Nature Reviews Electrical Enginee... » read more

2.5D + 3D = “3.5D”!
By Reela Samuel - 07 May, 2026 - Comments: 0

The semiconductor industry is no longer defined solely by transistor scaling. As Moore's law decelerates, advanced packaging has become the primary lever for achieving system-level performance gains. Within this landscape, the equation 2.5D + 3D = 3.5D—defying the instincts of basic math and physics—captures a pivotal architectural evolution: one that balances performance, manufacturabilit... » read more

Panel-Level Packaging’s Second Wave Meets Engineering Reality
By Gregory Haley - 16 Apr, 2026 - Comments: 0

Key Takeaways Panel-level packaging is arriving not because the engineering is ready, but because wafer-level economics are breaking down. Glass improves the warpage and dimensional stability problems of organic substrates but introduces a different class of failure modes that require materials solutions, not process adjustments. The central challenges of panel-level processing are m... » read more

The Thermal And Power Realities Of The AI Era
By Rafael Tudela - 16 Apr, 2026 - Comments: 0

The rapid growth of AI has created a surge in the global energy consumption at a rate never seen before. Today, data centers account for approximately 415 terawatt-hours (TWh) of electricity globally. To put this into perspective, the annual energy consumption of the United Kingdom in 2023 measured at 309 TWh. The International Energy Agency (IEA) projects data centers’ energy consumption wil... » read more

What’s Failing At The Interface
By Gregory Haley - 07 Apr, 2026 - Comments: 0

Key Takeaways The interface is where failures in advanced packaging become visible, but it's increasingly not where they originate. Weak interfaces often don't fail at time zero, but they do degrade due to parametric drift and margin erosion that binary test screens miss entirely. The temporary test interconnect is the largest variable in the measurement chain and must be controlled ... » read more

Challenges In Scaling Chips To 2nm And Below
By Ed Sperling - 30 Mar, 2026 - Comments: 0

Key Takeaways Scaling to 2nm and below continues due to power improvements per watt, but progress is much more challenging and costly. Solutions to problems often create other problems due to less margin for tradeoffs, often requiring larger interposers, more chiplets, and more complex packages. New levels of precision are required throughout the design-through-manufacturing flow, re... » read more

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