tag: hybrid bonding

Advancing Heterogeneous Integration Through Industry Roadmap Improvements
By Ravi V. Mahajan - 21 May, 2026 - Comments: 0

Heterogeneous integration requires comprehensive roadmaps to support collaboration across the design and manufacturing of the next generation of semiconductor products and the systems they support. A global team of researchers from a broad spectrum of industry, academia, and research institutes led by Intel has published a perspective in the March 2026 issue of Nature Reviews Electrical Enginee... » read more

2.5D + 3D = “3.5D”!
By Reela Samuel - 07 May, 2026 - Comments: 0

The semiconductor industry is no longer defined solely by transistor scaling. As Moore's law decelerates, advanced packaging has become the primary lever for achieving system-level performance gains. Within this landscape, the equation 2.5D + 3D = 3.5D—defying the instincts of basic math and physics—captures a pivotal architectural evolution: one that balances performance, manufacturabilit... » read more

Panel-Level Packaging’s Second Wave Meets Engineering Reality
By Gregory Haley - 16 Apr, 2026 - Comments: 0

Key Takeaways Panel-level packaging is arriving not because the engineering is ready, but because wafer-level economics are breaking down. Glass improves the warpage and dimensional stability problems of organic substrates but introduces a different class of failure modes that require materials solutions, not process adjustments. The central challenges of panel-level processing are m... » read more

The Thermal And Power Realities Of The AI Era
By Rafael Tudela - 16 Apr, 2026 - Comments: 0

The rapid growth of AI has created a surge in the global energy consumption at a rate never seen before. Today, data centers account for approximately 415 terawatt-hours (TWh) of electricity globally. To put this into perspective, the annual energy consumption of the United Kingdom in 2023 measured at 309 TWh. The International Energy Agency (IEA) projects data centers’ energy consumption wil... » read more

What’s Failing At The Interface
By Gregory Haley - 07 Apr, 2026 - Comments: 0

Key Takeaways The interface is where failures in advanced packaging become visible, but it's increasingly not where they originate. Weak interfaces often don't fail at time zero, but they do degrade due to parametric drift and margin erosion that binary test screens miss entirely. The temporary test interconnect is the largest variable in the measurement chain and must be controlled ... » read more

Challenges In Scaling Chips To 2nm And Below
By Ed Sperling - 30 Mar, 2026 - Comments: 0

Key Takeaways Scaling to 2nm and below continues due to power improvements per watt, but progress is much more challenging and costly. Solutions to problems often create other problems due to less margin for tradeoffs, often requiring larger interposers, more chiplets, and more complex packages. New levels of precision are required throughout the design-through-manufacturing flow, re... » read more

Advanced Packaging Limits Come Into Focus
By Gregory Haley - 19 Mar, 2026 - Comments: 0

Key Takeaways: Packaging is now a performance variable. Substrate, bonding, and process sequence determine what can be built at scale. Warpage underlies most advanced packaging failures and gets harder to control as package sizes grow. Every proposed solution, such as glass, panel processing, and backside power, solves one problem while creating another. Moore's Law has shif... » read more

Detecting Chemical Variability At Advanced Nodes
By Gregory Haley - 10 Mar, 2026 - Comments: 2

Key Takeaways Yield loss is increasingly driven by molecular variability in thin films, interfaces, and contamination rather than visible defects. Reliability issues often appear first as parametric drift or margin erosion under workload and thermal stress. Detection requires correlating molecular metrology, embedded electrical telemetry, and AI-driven wafer inspection. As s... » read more

Wafer-on-Wafer Hybrid Bonding: Reticle Placements To Achieve Efficient NW Topologies (ETH Zurich)
By Technical Paper Link - 09 Mar, 2026 - Comments: 0

Researchers from ETH Zurich published the new technical paper "Network Design for Wafer-Scale Systems with Wafer-on-Wafer Hybrid Bonding." Abstract "Transformer-based large language models are increasingly constrained by data movement as communication bandwidth drops sharply beyond the chip boundary. Wafer-scale integration using wafer-on-wafer hybrid bonding alleviates this limitation by p... » read more

Making Hybrid Bonding Better
By Laura Peters - 02 Mar, 2026 - Comments: 0

Key Takeaways Fab processes are optimizing for cleanliness, planarity, and high bond quality. Nanotwinned copper and SiCN PVD enable lower anneal and deposition temperatures for HBM. A thin, protective layer helps preserve the Cu/dielectric during aggressive processes. The future of semiconductor manufacturing is no longer dependent just on shrinking features. Instead, chipm... » read more

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