Advanced Packaging Limits Come Into Focus


Key Takeaways: Packaging is now a performance variable. Substrate, bonding, and process sequence determine what can be built at scale. Warpage underlies most advanced packaging failures and gets harder to control as package sizes grow. Every proposed solution, such as glass, panel processing, and backside power, solves one problem while creating another. Moore's Law has shif... » read more

Detecting Chemical Variability At Advanced Nodes


Key Takeaways Yield loss is increasingly driven by molecular variability in thin films, interfaces, and contamination rather than visible defects. Reliability issues often appear first as parametric drift or margin erosion under workload and thermal stress. Detection requires correlating molecular metrology, embedded electrical telemetry, and AI-driven wafer inspection. As s... » read more

Wafer-on-Wafer Hybrid Bonding: Reticle Placements To Achieve Efficient NW Topologies (ETH Zurich)


Researchers from ETH Zurich published the new technical paper "Network Design for Wafer-Scale Systems with Wafer-on-Wafer Hybrid Bonding." Abstract "Transformer-based large language models are increasingly constrained by data movement as communication bandwidth drops sharply beyond the chip boundary. Wafer-scale integration using wafer-on-wafer hybrid bonding alleviates this limitation by p... » read more

Making Hybrid Bonding Better


Key Takeaways Fab processes are optimizing for cleanliness, planarity, and high bond quality. Nanotwinned copper and SiCN PVD enable lower anneal and deposition temperatures for HBM. A thin, protective layer helps preserve the Cu/dielectric during aggressive processes. The future of semiconductor manufacturing is no longer dependent just on shrinking features. Instead, chipm... » read more

Catching Critical Defects In TSVs And Stacked Chips


Key Takeaways Variation is becoming a bigger problem in multi-die assemblies with TSVs and hybrid bonding. Multi-modal approaches are required to test these devices. AI plays a role in improving defect capture rate and distinguishing between yield-killing and false positives. New methods for interconnecting devices using through-silicon vias (TSVs) and hybrid bonding in stac... » read more

Chiplet Fundamentals For Engineers: eBook


Multi-die assemblies are the next phase of Moore's Law, scaling up and out  to improve performance and add flexibility into designs. By decomposing SoCs into building blocks, yield improves for the individual dies and overall performance increases because a chip is no longer bound by reticle limits. But this is much harder than it sounds. Chiplets don't just snap together like LEGOs, and so... » read more

Surface Metrology for Hybrid Bonding in Advanced Semiconductor Packaging


Achieving a reliable hybrid bond requires both surfaces to be pristine. To support this requirement, metrology methods such as atomic force microscopy (AFM) and atomic force profilometry (AFP) are critical for surface characterization and process optimization. AFM delivers localized, high-resolution surface measurements, while AFP provides complementary large-area topography scans that ... » read more

HBM4 Sticks With Microbumps, Postponing Hybrid Bonding


The next generation of high-bandwidth memory, HBM4, was widely expected to require hybrid bonding to unlock a 16-high memory stack. A JEDEC move made that unnecessary with this generation, but it’s merely a postponement, not a cancellation. HBM has been in high demand for AI in data centers — especially for training. Data movement dominates energy consumption, and high-bandwidth memories... » read more

AFM-Based Protocol for Characterizing the Incipient Stages of Plasticity on Hybrid Bonding-Ready Copper Pads (NIST, Intel, Colorado School of Mines)


A new technical paper titled "Probing the Nanoscale Onset of Plasticity in Electroplated Copper for Hybrid Bonding Structures via Multimodal Atomic Force Microscopy" was published by researchers at the National Institute of Standards and Technology, Intel, and Colorado School of Mines. Excerpt  "The slowdown of Moore’s law has elicited a paradigm shift whereby shrinking of in-plane dim... » read more

3D-IC Market Outlook: Technology Roadmaps, Readiness, And Design Implications


The 3D-IC market outlook is entering a decisive phase as the semiconductor industry transitions beyond the limits of traditional Moore's Law scaling. As performance, power efficiency, and system complexity outpace what planar integration can deliver economically, vertical integration and heterogeneous system design are no longer experimental; they are becoming foundational. Advanced packagin... » read more

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