But the inability to utilize leading-edge process nodes has created opportunities for small and midsize chip developers in multi-die design, along with some sophisticated architectural design tradeoffs.
Key Takeaways:
The benefits of device scaling are slowing, but the race to the next nodes continues unabated. Yet it’s unclear how many companies will be able to take advantage of the latest technology nodes, at least in the short term, because large systems companies are consuming nearly all the available capacity.
Leading-edge nodes provide the highest profit margins for foundries, and demand currently exceeds supply by a wide margin. The shift to nanosheets at 2nm and below offers lower power and less gate leakage, allowing more transistors to be packed into a given area for improved performance. This is particularly attractive to AI data centers, which have a nearly insatiable demand for speed.
For the most part, that excludes all but the biggest chipmakers. Even large chipmakers developing advanced-node chiplets may have trouble getting their chips manufactured quickly enough to be competitive. TSMC controls the majority of advanced-node supply and prioritizes large-volume orders from tech giants like Apple, Nvidia, and Broadcom, according to industry sources, although that could change as Intel Foundry and Samsung ramp up production.
Still, opportunities are opening up around the sides as designs shift from planar SoCs to systems-in-package with chiplets developed using different process technologies.
“Everyone has realized there’s a diminished return on investment for scaling everything,” said Rob Knoth, senior group director for strategy and new ventures at Cadence. “Some of the analog stuff is great, sitting on digital stuff. Sure, cram it on there, get your scaling. Then there’s this rise of a boutique flavor of advanced packaging — 2D, 2.5D, 3D. We’re going to have loop quantum gravity in there at some point, and it’s all happening at the same time. Everybody who either wants to build a fancy AI processor and needs the advanced packaging because of the data bandwidth that’s on there, because of what they’re trying to achieve, or you’re someone who’s just trying to make a piece of silicon that is taking advantage of scaling, they’re going to be naturally looking at these complex packages. Or you’re someone who maybe was targeting one of those big nodes, but can’t get the capacity, so chiplets plus packaging plus what can we tape out? That gives you a path. What that all means is there’s a greater demand for advanced packaging. There isn’t a one-size-fits-all solution there. It’s incredibly application-specific. It’s very cost-sensitive. It’s very tool sensitive. It’s very IP sensitive. It’s similar to what we saw when finFET first came out. When finFET first came out, EDA vendors made the tools by working with the first movers onto the node, working with the major foundries. You saw a very small number of people making designs at finFET. At the time, the narrative was, ‘Only five companies on the planet are ever going to do finFET.’ We’re going to see the same trend when it comes to packaging. The first movers are not just going to be there, but they’ve been there. They’re blazing the trail. They’re coming out with things like TSMC’s 3Dblox, and the other foundries have their own flavors of that.”
The EDA industry has been collaborating with industry leaders to advance these initiatives. For example, Charlie Kawwas, president of the semiconductor solutions group at Broadcom, highlighted the variety and collaboration with Cadence in this area. Knoth expects the first phase to consist of a concentrated amount of business led by major foundries and ASIC firms that have the necessary expertise and tools, as well as a broad range of IPs. “The EDA industry’s role is to democratize technology, automate processes, and simplify tasks, enabling fast followers to quickly adopt similar strategies. This pattern mirrors what occurred with FinFET technology—it’s now happening again with advanced packaging.”
So where does this leave the smaller developers that aim to compete in advanced AI and specialized application markets? And how is this changing the landscape of design innovation?
“The reality is that we are getting to more and more complex scenarios for smaller companies, because the costs of advanced packaging are going up,” Nandan Nayampally, chief commercial officer at Baya Systems, observed. “There are two or three problems in that list. First, is it just advanced packaging, like TSMC’s CoWoS, etc., and all the chiplets are yours or co-developed? Or are the chiplets that you may be using coming from multiple vendors? That adds enough of a wrinkle to take ownership of that. And when this expensive process is done, if something fails, how do you solve that? Who’s underwriting that problem? That’s another reason why the big packaging houses will not take smaller design houses, where you’re having potentially multiple players providing chiplets, because then we don’t know what causes the failure. It happens. But who’s liable? There’s a barrier of cost that is beginning to create a wall on that. Now, with the whole new approach that TSMC is pushing on 3nm, etc., on advanced packaging, it is potentially a workaround. But then it comes to capacity and time, and they’re always going to be leaning toward the big guys that have massive volume and buying power, taking up most of that. On the map of TSMC’s top-end customers, when you see companies like Marvell at 2% of the whole thing, you know how big the big are, and that’s where the bread is buttered. It’s going to be tough unless you have smaller design houses and the imecs, and the like, which can make some of this possible. But the challenge is certainly there, where the costs and volumes are getting to a point where the small guys don’t have as much of a revenue share and mindshare to justify some of the packaging team’s time.”
Major players rule foundry capacity
Gaining access to state-of-the-art semiconductor manufacturing is now dictated more by capacity and long-term agreements than by pure technology choice. Technological capability is just a prerequisite. Getting that into the latest foundry process can take anywhere between 6 and 12 months, or even longer in some cases.
“These days, the first question I’ll have is whether I can actually reserve enough wafers at that node at TSMC,” noted Pratyush Kamal, director for central engineering solutions at Siemens EDA. “Impossible today, probably. And that’s why everybody is forced to go back to Samsung. Nvidia has so much money, they’ll just buy all the capacity. Apple also has so much money, they’ll buy all the capacity at 2nm, and they’re doing it.”
Adding to the challenge, foundries are not transparent about critical yield and defectivity data. Companies must rely on their own experts to estimate reasonable pricing and negotiate with the fabs.
“Fabs don’t give you insight into their defectivity numbers,” Kamal said. “That’s why you have your own PhDs… to guess how much the price to TSMC should be, and whether TSMC charging $30,000 makes sense or not. Then you go negotiate.”
Small and mid-size chip developers have their own challenges. “It does get complicated, especially for a smaller company that wants to get into advanced packaging,” said Shawn Nikoukary, senior director of SoC engineering at Synopsys. “There’s a lot of overhead on tools, and there’s a lot of overhead on the skills they need to develop. So it is challenging.”
In this context, custom chiplets may be a credible option. It can be more cost-effective to add functionality with a specialized chiplet than trying to cram everything into a monolithic die. “If they were to go with a partitioning approach in a multi-die system with the chiplets, they could have more flexibility as well as modularity, because now they can mix and match different dies on a package,” said Esha Dubey, hardware engineering manager at Synopsys. “They could have one processor on one node, the I/O on an older node, and so on. It’s a lower-cost approach. That’s another reason why advanced packaging is an offering that would work for most.”
Taking a multi-die approach also may help to streamline design decisions and tradeoffs based on the relationship a company has with a foundry. “Some companies are TSMC houses, some are Samsung, some work with smaller OSAT vendors. So it can depend on the handshake that the company has with a particular foundry. If it’s a TSMC house, then they would stick with technologies like CoWoS for a silicon bridge. It could be either a silicon interposer, a bridge, or a fan-out. Whereas, if it’s Samsung, then they have their own Cube series. And if they want to go to Intel Foundry, then it comes to an EMIB (Embedded Multi-Die Interconnect Bridge),” Dubey said.
Foundries offer similar technologies. TSMC, Samsung, Intel, and ASE all have their own RDL fan-out versions with a silicon bridge:
“They’re all, in a way, competing with each other,” Dubey noted. “That is also a decision-making step left to the architect to select which one works best.”
Keeping EDA tools, equipment, and processes in sync is another challenge. “Every time we think we have everything set up for this technology, and new technology comes from the foundry, we need to revamp the assembly design kits, process design kits, and tech files,” Dubey said. “Before, it used to be a set of design rules that you would type into a substrate design. The engineer would do that, but now it’s a lot more complicated to support all the different technologies. It’s challenging, especially for small companies. We are in the middle of everything, but I would understand for a small startup, for example, that has an idea and wants to package it. That used to be easy before, but now they need to really worry about it.”
This means there is even more pressure to find a cost-effective way to do the project, look at which foundry has the best offering for their needs, study the design rules, and go from there.
For many, the decision is about whether to disaggregate an SoC into a multi-die/advanced package, and what the ROI may be for that approach. “‘What’s the ROI going to be?’ There are risk factors, and then there are costs,” said Stephen Slater, integrating manager for EDA products at Keysight EDA. “They look at how much the cost envelope for the final packaged product is that the market is willing to accept. What are the performance specs? What are the pros and cons? It’s a small committee of people who are deciding whether this is the right technology inflection point for them to take the plunge, or whether they’re going to do things the traditional way this time, then move to advanced packaging for the next generation of solutions. There are those for whom chiplets are the only option, and there are those for whom the technology is interesting for their future, and they are planning pilot projects accordingly. And much of this economic choice comes down to the cost estimates that they get provided from TSMC, and the increasing confidence in the reliability of the process. That comes down to how mature the process is and the heat management during assembly and during operation. Too much heat cycling will weaken the interconnects over time.”
Model order reduction for the architect making these decisions is a critical factor in many cases. “We look at a very high level and have to make a lot of decisions very early on,” said Siemens EDA’s Kamal. “Most of it is sourcing-related. A lot of pricing is involved in the partitioning decision cost, because with the package, you’re also shifting the burden of test to a lot of tests that can still be done at the package, at the die level, but more tests are now required to be done at the advanced package, post advanced packaging, and there is a cost of advanced packaging, so your amount of scrap goes up. You have to account for all of that. Test time goes up, and there are equations to translate that into dollars. Everything in the end does come down to the dollar.”
What about the super creative, interesting startups that are doing neat things? Will those ideas be lost to the ether because of the inability to get into the foundry? The general consensus is, never say never.
“Every time you think that happens, there’s a workaround or there’s a disruption that comes along,” said Baya Systems’ Nayampally. “I’m a firm believer that there will be a disruption coming that enables smaller players to have a path to market. I’m not seeing it yet, but it may come in from slightly more mature nodes first. For a lot of the players, unless they’re trying really hard to go into very high-volume solutions at 3nm and 2nm, where the performance is to keep up with the big SiPs, that’s where the tough part is. But if you can be on the trailing edge and offer lower-cost solutions, that’s where the architectural discussion comes in. Can I be three nodes behind and give you the same performance, but at 1/5 the cost? That then sets up a model whereby, if I’m now doing multiple packages, multiple chiplets, and packaging that’s on a mature node that’s actually gone through it, then it can go further along. Maybe there is an auxiliary set of companies that have enough of a business model, enough volume, and enough of a return to go build those. Every time there has been this consolidation, there’s also been a disruption, and I expect that we will come to that.”
Not out of the game
William Wang, CEO of ChipAgents, believes that while today’s constraints are real, they don’t eliminate the smaller players. “It changes how they compete,” he said. “The opportunity is to move faster, design smarter, and avoid costly iteration cycles.”
This is where ChipAgents is positioned. “By automating large parts of design, verification, and root-cause analysis, it lowers the engineering overhead required to build complex chips. That effectively democratizes chip development. Smaller teams can iterate like much larger ones, making them viable even without privileged access to leading-edge capacity,” Wang explained.
Despite these challenges and the evolving landscape, industry experts point out that the market is not entirely closed to smaller players. The dynamics have shifted, but there are still avenues for innovation and competition, especially for those able to adapt quickly and leverage new strategies.
“Currently, there are four main foundry companies — TSMC, Samsung, GlobalFoundries, and Intel,” said Satish Radhakrishnan, head of GTM at Vinci. “TSMC’s capacity is limited because major tech companies are ordering ahead. This allows the smaller companies to do two things. Go for slightly older technology or with another foundry such as Samsung, Intel, or GlobalFoundries. Advanced nodes are also very expensive due to the new equipment used to enable them. Multiple companies have shown that optimized design can achieve good performance from older nodes. For smaller chip developers, getting product to market so customers can experience it is key to establishing a foothold and slowly gaining market share through good performance.”
Not all applications need to move to advanced nodes, but some definitely do.
“Top-end GPU machines or top-end cell phones currently take the first use of advanced nodes,” Radhakrishnan said. “However, the top-end product’s high price means many companies still rely on older technologies. For example, Nvidia’s H200, which is now three generations old, is still popular. But a newer company with better performance for the same or lower price can definitely play a strong role in the market.”
Bringing all of this to bear, only the largest, most financially powerful companies can reliably secure leading-edge wafers and negotiate from a position of strength. All others are pushed to alternative foundries and are forced to make more conservative architectural and packaging choices under stricter economic constraints.
In practice, this means technology roadmaps are being set by a handful of mega-customers, because they are the only ones that can pre-buy and lock up leading-edge capacity, absorb the high wafer cost and extreme yield risk, and fund the in-house modeling and negotiation expertise that fabs respond to. Everyone else is effectively priced out of shaping the bleeding edge and must use second-tier or older nodes, often at Samsung or lagging nodes at TSMC. These developers must compensate with more conservative architectures and packaging choices, such as fewer chiplets, less aggressive 3D, and less risky partitioning, and more focus on cost, yield, and predictability over performance leadership.
Conclusion
At advanced nodes, economic power has become a de facto design constraint. Only the richest companies can fully exploit and shape the newest processes, while everyone else is pushed to second-tier options, where architecture and packaging are dictated less by what’s technically possible than by what they can afford. But this has also opened new opportunities for unique advanced packaging techniques and chiplets developed at older process nodes.
Node choice, partitioning, and packaging are now determined as much by who can secure and afford leading-edge capacity as by what is technically possible. Decisions around node selection, partitioning, packaging, and redundancy are now yield- and cost-driven, with advanced packaging and test economics baked into every tradeoff. In practice, the chip architect’s role has become one of system-level co-design with stringent manufacturing, thermal, and economic constraints, while at the same time encouraging new creativity in multi-die technologies.
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