tag: semiconductor manufacturing

Optimizing Curvilinear OPC: Vector- Based Site and Anchor Decoupling
By Siemens EDA - 24 Jun, 2026 - Comments: 0

As semiconductor technology advances to sub-5 nm nodes, curvilinear mask features are essential for pattern fidelity but challenge traditional OPC methods. Siemens introduces an advanced vector-based site and anchor decoupling framework that independently and dynamically controls OPC fragmentation and optimization. This innovation significantly boosts process window robustness, speeds up mask r... » read more

Advancements In Atomic-Scale Plasma Processing
By Technical Paper Link - 22 Jun, 2026 - Comments: 0

Researchers from Nagoya University, Boise State University, Korea Institute of Fusion Energy, Hitachi High-Tech Corp. and Princeton Plasma Physics Laboratory published a technical paper titled “Recent Progress in Atomic-Scale Controlled Plasma Processing.” Abstract Excerpt: “Atomic-scale control in plasma processing is becoming increasingly critical for fabricating of advanced semic... » read more

Event-Driven RL Targets Long-Horizon Fab Control
By Technical Paper Link - 21 Jun, 2026 - Comments: 0

Researchers from Politecnico di Milano and STMicroelectronics published a technical paper titled “Event-Driven Reinforcement Learning Enables Long-Horizon Control in Semiconductor Fabrication.” The paper proposes a deep reinforcement learning framework for multi-objective policy optimization in semiconductor manufacturing, where heterogeneous wafers move through hundreds of process steps... » read more

Using Graph Attention for Virtual Metrology in Semiconductor Manufacturing (Intel Foundry, ASU)
By Technical Paper Link - 02 Jun, 2026 - Comments: 0

Researchers from Arizona State University and Intel Foundry have published “Graph Attention-Based Virtual Metrology for Film Deposition Processes in Semiconductor Manufacturing”. Abstract “Artificial intelligence-driven semiconductor manufacturing increasingly operates at nanometer and angstrom scales, where precise process control depends on accurate and timely metrology. Howeve... » read more

Process Variation In The Era Of Scaling: Improving Uniformity With Dummy Fill
By HJ Kim - 21 May, 2026 - Comments: 0

As semiconductor patterning continues to scale, even small layout nonuniformities can lead to noticeably different process outcomes. Real chip layouts contain a mix of dense regions, large open regions, and isolated features. As a result, the etch process encounters different “local environments” across the wafer. Even with the same process settings (or recipe), some areas may etch mo... » read more

AI & Energy: Bending The Curve
By Pushkar Apte - 21 May, 2026 - Comments: 0

By Pushkar P. Apte and Melissa Grupen-Shemansky Artificial intelligence (AI) is scaling at a pace that is reshaping semiconductor roadmaps, data center design, and long-term infrastructure strategy. AI promises many economic and social benefits, but the growth comes with an escalating demand for power, and energy has emerged as a major challenge. The AI & energy challenge AI training c... » read more

Complete End-To-End Closed-Loop Product Yield Ramp And Learning
By Guy Cortez - 12 May, 2026 - Comments: 0

By Guy Cortez and Maheshwaran Jothi Yield ramp has always been a concern in semiconductor manufacturing: systems companies need confidence that devices meet quality targets before shipment, and chipmakers need to reach yield entitlement quickly to control cost and supply. While this has never been easy, advanced nodes are raising the bar again. First, designs are larger and more heterogen... » read more

Foundry Capacity Is Limiting Who Competes At Leading Edge Nodes
By Ann Mutschler - 30 Apr, 2026 - Comments: 0

Key Takeaways: Leading-edge node access is increasingly reserved for hyperscalers, squeezing smaller chip developers. Chiplets and advanced packaging offer a path forward, but raise cost, complexity, and risk — especially for smaller teams. Chip architecture is now driven as much by capacity, yield, and economics as by technical goals. The benefits of device scaling are sl... » read more

When Semiconductor Materials Misbehave
By Gregory Haley - 27 Apr, 2026 - Comments: 0

Key Takeaways Material behavior in production depends on the process context that no development environment can fully replicate. In advanced packaging, the interactions that cross domain boundaries are increasingly where failures originate. The most accurate materials data is also the most commercially sensitive, leaving simulation models calibrated against generic inputs rather tha... » read more

TSV Complexity Leads To Manufacturing Bottleneck
By Laura Peters - 22 Apr, 2026 - Comments: 1

Key Takeaways: Through-silicon vias are the biggest enabler of 3D chip stacking and chip-to-PCB connections through silicon interposers. The AI boom is causing HBM and advanced assembly shortages, straining the supply chain. Optimization around etch, fill and reveal help reduce TSV cost. Through-silicon vias (TSVs) provide essential interconnects between DRAM dies inside hig... » read more

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