CHIPS For America’s National Semiconductor Technology Center (NSTC) Program

A roadmap to increase the manufacturing competitiveness of the U.S. semiconductor industry.


At this year’s Design Automation Conference, Jay Lewis, director of CHIPS for America National Semiconductor Technology Center (NSTC) Program, gave a presentation on the status and direction of the Center, its priorities for this year and how the NSTC can change the long-term trajectory for innovation.

Fig. 1: Dr. Jay Lewis, director of NSTC Program, CHIPS R&D Office at the Dept. of Commerce.

It’s no secret that the U.S. has fallen behind in leading edge semiconductor manufacturing and Jay referenced the President’s Council of Advisors on Science and Technology (PCAST) report titled, “Ensuring Long‐term U.S. Leadership in Semiconductors,” from January 2017. Jay noted that the report mentioned, “any presumption by U.S. policymakers that existing market forces alone will yield optimal outcomes – particularly when faced with substantial industrial policies from other countries – is unwarranted” and “The United States, in contrast with some major competitors, provides companies the ingredients necessary to innovate rather than simply cutting costs for existing technologies. Historically, U.S. government-sponsored research and development (R&D) has been essential to driving semiconductor innovation – but that support will be unsustainable if industry is hollowed out.” This report led to the Electronics Resurgence Initiative (ERI) which consisted of an initial $75M of funding and then $1.5B to be spread over five years.

Jay also mentioned TSMC’s CEO, C.C. Wei’s reply to Morgan Stanley Research Analyst, Charlie Chan, about Intel’s 18A. We reported this back in January, “C.C. Wei replied that their customer’s newest technology will be very similar or equivalent to TSMC’s N3P. TSMC further checked again with all the specs, all of the possible published material in the technology, transistor technology and everything and that his comment stays the same. Dr. Wei also felt that TSMC still holds a big advantage in technology maturity too. TSMC’s N3 will be in its third year of production in 2025 when the other IDM is claiming to go into production.” Jay didn’t take any position on the comparison, but simply noted that this is what’s been reported in the press.

Fig. 2: Intel Foundry process roadmap. (Source: Intel Foundry)

Figure 2 shows an Intel Foundry process roadmap that was publicly announced back in February. It was also reported here that Intel 10A would be in development/production in 2027 (not volume production). This should keep things interesting in terms of whether Intel can keep these schedules and close the gap with TSMC.

This also plays into the slide behind Jay shown in figure 3 below, that states that one of the goals is to go from a present day 0% of the leading-edge manufacturing occurring in the U.S. to a 20% share in the U.S. by 2030. This 20% target is also part of the ERI 2.0 plan. Note that this doesn’t necessarily mean that all that manufacturing would necessarily be performed by Intel either, but it seems likely that to get to that 20% number, Intel would have to be some significant portion of that 20%.

Fig. 3: Outcomes.

Jay pointed out that there is also worldwide recognition of semiconductor importance, with other countries like Japan, South Korea, and Germany having multi-billion-dollar incentives in place. A Japanese company, Rapidus, earlier this month announced an agreement with IBM to expand its collaboration beyond IBM’s 2nm fabrication process technology to include chiplet packaging. There are reports that the Japanese government is set to kick in approximately $3.9B to help support the Japanese foundry venture. It’s interesting to see that at a time when the U.S. is fighting to regain leading edge process market share that an advanced technology process that appears to have been largely researched and developed in Albany, NY is heading over to the other side of the Pacific Ocean for larger scale manufacturing.

From a technology standpoint, Jay called out five key areas: Logic, Advanced Packaging, AI at Scale, Memory, and Interconnect. Certainly, AI is an important driver as there seems to be an insatiable demand for AI chips and every new node promises more compute capability for less energy. Part of that improved efficiency is gained from the use of chiplets and advanced packaging. Jim Keller’s Monday keynote touched on this and was again reinforced by Gary Patton’s Tuesday keynote with Intel Foundry positioning itself as a systems foundry. This realization inside the industry likely was also a key motivator for Rapidus to extend its collaboration with IBM to include chiplet packaging. Fabricating ICs on advanced process nodes is a necessary but not sufficient condition for success in this market space.

Regarding interconnect technologies, Jay said that copper is the “silicon of interconnects” and that the industry would likely squeeze every last bit that it can out of copper before moving to something else, perhaps something like Ruthenium.

Fig. 4: CHIPS for America $52B distribution plan. (Source: NIST)

Figure 4 shows how the $52B in funding will be spread across production and R&D programs. Based on the 5 key areas pointed out earlier, figure 5 below shows the R&D programs. The CHIPS National Semiconductor Technology Center (NSTC) Program will be operated by Natcast which is an independent nonprofit organization. A roadmap is available online as is a vision and strategy paper for the NSTC. Jay mentioned that a near term goal is standing up Natcast and the slide in figure 4 is from a webinar presentation, “An Update on the National Semiconductor Technology Center (NSTC),” that was authored by Jay and Natcast’s new CEO, Deirdre Hanford.

Fig. 5: CHIPS R&D programs. (Source: NIST)

Fig. 6: The future.

Figure 6 shows a summary slide of the future direction for NSTC, broken down by the infrastructure and support programs and how that shapes up for startups, academia, foundries and fabless semiconductor companies. This all puts together a roadmap to once again increase the manufacturing competitiveness of the U.S. semiconductor industry. As is the case with many plans, success will in large part now be determined by the execution.

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