TSMC Reports 4Q2023 Earnings: N2 Still On Track For 2025 Production

3nm is ramping, followed by 2nm next year.


TSMC reported their 4th quarter and end of year financial numbers for 2023. Year over year, net revenue was down 4.5% to NT$2,161.74 billion, but quarter over quarter revenue was essentially flat at NT$625.52 billion, so it appears that as 3nm is ramping up that revenue is improving.

For the fourth quarter, 3nm contributed 15% of TSMC’s total wafer revenue, up from 6% in the third quarter of 2023. 5nm and 7nm accounted for 35% and 17% respectively in the fourth quarter and the advanced technology nodes (7nm and below) accounted for 67% of the total fourth quarter wafer revenue, up from 59% in the third quarter. For the year, 3nm, 5nm and 7nm contributed 6%, 33% and 19% respectively to the total wafer revenue. The graph below shows how 5nm picked up revenue while 7nm dropped and they sort of mirror each other over an imaginary line drawn at ~26%. The additional advanced technology revenue was realized by 3nm contributions in Q3 and Q4.

Figure 1. Percentage of Total Wafer Revenue by Technology

Figure 1. Percentage of Total Wafer Revenue by Technology

By platform, net revenue percentages for High Performance Computing (HPC) and Smartphone led the way with 43% share each. North America led net revenue by Geography with a 72% share.

TSMC CEO, C.C. Wei, said that TSMC 3nm is the most advanced PPA and transistor technology node in the world. It has led to success in the HPC and Smartphone markets and TMC expects 2024 to be a healthy growth year for TSMC, supported by the continued strong ramp of their industry-leading 3-nanometer technologies, strong demand for the 5-nanometer technologies and robust AI-related demand.

Dr. Wei said that N3E further leverages TSMC’s strong foundation of N3 to extend the N3 family with enhanced performance, power and yield. N3E has already entered volume production in the fourth quarter of 2023. Supported by robust demand from customers in both smartphone and HPC applications, revenue from 3-nanometer technology is expected to more than triple in 2024 and account for a mid-teens percentage of TSMC’s total wafer revenue.

TSMC also continues to provide further enhancements of its N3 technology, including N3P and the N3X. With their strategy of continuous enhancements of 3-nanometer process technologies, TSMC expects strong multiyear demand from customers and are confident that their 3-nanometer family will be another large and long-lasting node for TSMC.

TSMC’s 2-nanometer technology will adopt a narrow sheet transistor structure and TSMC claims that it will be the most advanced semiconductor technology in the industry in both density and energy efficiency when it is introduced in 2025. C.C. Wei said that their N2 technology development is progressing well with device performance and yield on track or ahead of plan and that N2 is on track for volume production in 2025 with a ramp profile like N3. As part of their N2 technology platform, TSMC is also developing N2 with a backside power rail solution, that is better suited for specific HPC applications based on performance, cost, and maturity considerations. N2 with backside power rail will be available in the second half of 2025 to customers with production in 2026.

TSMC Chairman, Mark Liu, gave an update on fab construction outside of Taiwan. He said that TSMC is well on track for volume production of N4 (or 4-nanometer process technology) in the first half of ’25 and are confident that once TSMC begins operations, they will be able to deliver the same level of manufacturing quality and reliability in Arizona as from their fabs in Taiwan.

In Europe, TSMC plans to build a specialty technology fab in Dresden, Germany, focusing on automotive and industrial applications with their joint venture partners. TSMC continues to be in close communication with the German federal, state and city governments and their commitment to this project remains strong and unchanged. Fab construction is scheduled to begin in Q4 2024 this year.

Mark Liu also announced that he would be retiring from his position as Chairman of TSMC in June of 2024 and that Dr. C.C. Wei has been recommended to be his replacement.

Charlie Chan, Research Analyst from Morgan Stanley, asked about the comments about technology leadership, because TSMC’s competitor (and customer), Intel, states that their PPA is ahead of TSMC’s 2-nanometer and that even the cost is lower.

C.C. Wei replied that their customer’s newest technology will be very similar or equivalent to TSMC’s N3P. TSMC further checked again with all the specs, all of the possible published material in the technology, transistor technology and everything and that his comment stays the same. Dr. Wei also felt that TSMC still holds a big advantage in technology maturity too. TSMC’s N3 will be in its third year of production in 2025 when the other IDM is claiming to go into production.

Chairman Mark Liu added some color to this and said that he thought that C. C. has been very modest. “I think he’s claimed that our N3P is comparable to their 18A. We still affirm our statement. But I would like you to look at a different perspective. And what C. C. — what the other side claim might be right, but it’s only to their own product. An IDM typically optimize their technology for their own product, where foundry, us, we optimize our technology for our customers’ products, so that’s a big difference.”

A complete transcript of the conference call is available here.

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