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Adaptive Clocking: Minding Your P-States And C-States


Larger processor arrays are here to stay for AI and cloud applications. For example, Ampere offers a 128-core behemoth for hyperscalers (mainly Oracle), while Esperanto integrates almost 10x more cores for AI workloads. However, power management becomes increasingly important with these arrays, and system designers need to balance dynamic power with system latency. As we march year over year, t... » read more

Power Domain Implementation Challenges Escalate


The number power domains is rising as chip architects build finer-grained control into chips and systems, adding significantly to the complexity of the overall design effort. Different power domains are an essential ingredient in partitioning of different functions. This approach allows different chips in a package, and different blocks in an SoC, to continue running with just enough power t... » read more

Audio, Visual Advances Intensify IC Design Tradeoffs


A spike in the number of audio and visual sensors is greatly increasing design complexity in chips and systems, forcing engineers to make tradeoffs that can affect performance, power, and cost. Collectively, these sensors generate so much data that designers must consider where to process different data, how to prioritize it, and how to optimize it for specific applications. The tradeoffs in... » read more

Can Analog Make A Comeback?


We live in an analog world dominated by digital processing, but that could change. Domain specificity, and the desire for greater levels of optimization, may provide analog compute with some significant advantages — and the possibility of a comeback. For the last four decades, the advantages of digital scaling and flexibility have pushed the dividing line between analog and digital closer ... » read more

IP Industry Transformation


The design IP industry is developing an assortment of new options and licensing schemes that could affect everything from how semiconductor companies collaborate to how ICs are designed, packaged, and brought to market. The IP market already has witnessed a sweeping shift from a "design once, use everywhere" approach, to an "architect once, customize everywhere" model, in which IP is highly ... » read more

Week In Review: Auto, Security, Pervasive Computing


Automotive, mobility Cruise, General Motors’ self-driving car company, obtained a permit to charge for rides in San Francisco, according to a story in Reuters. The California Public Utilities Commission, the regulatory board that can approve permits, voted 4-0 to issue “the first Phase I Driverless Autonomous Vehicle (AV) Passenger Service Deployment permit in California to Cruise LLC to a... » read more

Enabling Big Chip AI Solutions Through Intelligent Clock Networks


Data centers, autonomous vehicles, and computer vision applications are pushing the limits of scalable AI compute. Data center chips face multi-trillion parameter models that continue growing every year. ADAS systems require flexibility and processing power for new model types, such as vision transformers. Edge AI solutions demand tight power budgets and the ability to process multiple models i... » read more

Low Earth Orbit Satellites For More Reliable Internet


Working from home may have reduced the stress of commuting, but it put a heavy strain on the power grid and ate into energy reserves. Still, with utilities such as electricity and water, it's possible to buy or borrow from adjacent grids or territories. The same cannot be said for internet service providers. They cannot just borrow from another service provider. Instead, their customers woul... » read more

Week In Review: Design, Low Power


Tools & IP Synopsys unveiled a new neural processing unit (NPU) IP and toolchain. DesignWare ARC NPX6 NPU IP scales from 4K to 96K MACs with power efficiency of 30 TOPS/Watt. A single instance offers 250 TOPS at 1.3 GHz on 5nm processes in worst-case conditions, or up to 440 TOPS by using new sparsity features, which can increase the performance and decrease energy demands of executing a n... » read more

Clocks Getting Skewed Up


At a logical level, synchronous designs are very simple and the clock just happens. But the clocking network is possibly the most complex in a chip, and it's fraught with the most problems at the physical level. To some, the clock is the AC power supply of the chip. To others, it is an analog network almost beyond analysis. Ironically, there are no languages to describe clocking, few tools t... » read more

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