Chip Industry Week In Review


SK hynix and TSMC plan to collaborate on HBM4 development and next-generation packaging technology, with plans to mass produce HBM4 chips in 2026. The agreement is an early indicator for just how competitive, and potentially lucrative, the HBM market is becoming. SK hynix said the collaboration will enable breakthroughs in memory performance with increased density of the memory controller at t... » read more

Staying Within The Margins


Last March I wrote an article called Squeezing the Margins that’s about a design that used an adaptive clocking scheme to keep the performance of a system high while simultaneously keeping the temperature below a specified maximum. Last August we looked at Managing Voltage Variation and how an adaptive clocking scheme could be used to manage dynamic voltage drop to maximize system performance... » read more

Sea Of Processors Use Case


Core counts have been increasing steadily since IBM's debut of the Power 4 in 2001, eclipsing 100 CPU cores and over 1,000 for AI accelerators. While sea of processor architectures feature a stamp and repeat design, per-core workloads aren't always going to be symmetrically balanced. For example, a cloud provider (AI or compute) will rent out individual core clusters to customers for specialize... » read more

The Rising Price Of Power In Chips


Power is everything when it comes to processing and storing data, and much of it isn't good. Power-related issues, particularly heat, dominate chip and system designs today, and those issues are widening and multiplying. Transistor density has reached a point where these tiny digital switches are generating more heat than can be removed through traditional means. That may sound manageable e... » read more

Brain-Inspired, Silicon Optimized


The 2024 International Solid State Circuits Conference was held this week in San Francisco. Submissions were up 40% and contributed to the quality of the papers accepted and the presentations given at the conference. The mood about the future of semiconductor technology was decidedly upbeat with predictions of a $1 trillion industry by 2030 and many expecting that the soaring demand for AI e... » read more

Remote Droop Detection And Response Use Case


While sea of processor architectures feature a stamp and repeat design, per-core workloads aren't always symmetrically balanced. For example, a cloud provider (AI or compute) will rent out individual core clusters to customers for specialized and varied workloads. However, this asymmetry, combined with rapid provisioning changes, can lead to global voltage droops on the SoC resulting in potenti... » read more

TSMC Reports 4Q2023 Earnings: N2 Still On Track For 2025 Production


TSMC reported their 4th quarter and end of year financial numbers for 2023. Year over year, net revenue was down 4.5% to NT$2,161.74 billion, but quarter over quarter revenue was essentially flat at NT$625.52 billion, so it appears that as 3nm is ramping up that revenue is improving. For the fourth quarter, 3nm contributed 15% of TSMC’s total wafer revenue, up from 6% in the third quarter ... » read more

Which Data Works Best For Voltage Droop Simulation


Experts at the Table: Semiconductor Engineering sat down to talk about the need for the right type of data, why this has to be done early in the design flow, and how 3D-IC will affect all of this, with Bill Mullen, distinguished engineer at Ansys; Rajat Chaudhry, product management group director at Cadence; Heidi Barnes, senior applications engineer at Keysight; Venkatesh Santhanagopalan, prod... » read more

Top500: Frontier Still On Top, Sunway Formally Reappears


New versions of the Top500 and Green500 lists have been released, and Frontier continues its reign at Number. 1. But a newcomer, Aurora, using Intel’s Sapphire Rapids, has entered at the Number 2 position with a “half-scale” system. Both machines are HPE Crays, with the former using AMD optimized third-gen EPYC 64C at 2.0GHz and AMD Instinct MI250X, while the latter uses Intel Xeon CPU... » read more

Analog Design Complicates Voltage Droop


Experts at the Table: Semiconductor Engineering sat down to talk about voltage droop in analog and mixed-signal designs, and the need for multi-vendor tool interoperability and more precision, with Bill Mullen, distinguished engineer at Ansys; Rajat Chaudhry, product management group director at Cadence; Heidi Barnes, senior applications engineer at Keysight; Venkatesh Santhanagopalan, product ... » read more

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