tag: 3nm

Accelerating Automotive Innovation: SRAM Compiler Breakthroughs for 5nm and 3nm SoCs
By Synopsys - 01 Apr, 2026 - Comments: 0

Modern automotive SoCs must deliver extreme performance, functional safety, and long‑term reliability — all under growing power and thermal constraints. This white paper explains how next‑generation Synopsys SRAM Compiler IP for TSMC N5A and N3A helps design teams meet these challenges with measurable gains in PPA, reliability, and system robustness. Why Read this White Paper: See... » read more

Extraction Challenges of CFET and Backside Power Delivery
By Siemens EDA - 25 Mar, 2026 - Comments: 0

The integration of complementary field-effect transistors (CFETs) and buried power rails (BPRs) is central to advancing semiconductor scaling for nodes at 3nm and below. CFETs achieve unprecedented device density by vertically stacking n-type and p-type transistors, while BPRs embed the power network within the silicon substrate to boost efficiency and minimize area usage. These advances drive ... » read more

Beyond BPD: Backside Clock and Signal Routing for Sub-3nm (UT Austin, Intel)
By Technical Paper Link - 17 Oct, 2025 - Comments: 0

A new technical paper titled "Beyond Backside Power: Backside Signal Routing as Technology Booster for Standard Cell Scaling" was published by researchers from University of Texas at Austin and Intel. Abstract "Advances in process technology enabling backside metals and contacts offer new Design-Technology Co-Optimization (DTCO) opportunities to further enhance power, performance, and area ... » read more

Manufacturing At The Limits
By Gregory Haley - 21 Aug, 2025 - Comments: 2

Hybrid bonding has been in production for several years, with mature flows capable of delivering robust yields using 10µm interconnects. At that scale, processes can tolerate hundreds of nanometers of overlay variation, modest differences in wafer bow, and particle sizes rivaling the interconnect height without catastrophic impact. Hybrid bonding is compatible with optical metrology, existing ... » read more

Why Thin Film Measurements Matter
By Laura Peters - 08 Apr, 2025 - Comments: 0

Semiconductor devices are becoming thinner and more complex, making thin deposited films even harder to measure and control. With 3nm node devices in production and 2nm nodes ramping toward first-silicon, the importance of precise film measurement is only growing in significance as fabs seek to maintain the performance and reliability of leading-edge devices. Whether it’s the read and writ... » read more

SRAM With Mixed Signal Logic With Noise Immunity in 3nm Nanosheet (IBM)
By Technical Paper Link - 24 Jan, 2025 - Comments: 0

A new technical paper titled "SRAM and Mixed-Signal Logic With Noise Immunity in 3nm Nano-Sheet Technology" was published by researchers at IBM T. J. Watson Research Center and IBM. Abstract "A modular 4.26Mb SRAM based on a 82Kb/block structure with mixed signal logic is fabricated, characterized, and demonstrated with full functionality in a 3nm nanosheet (NS) technology. Designed macros ... » read more

5 Novel Layout Design Methodologies For The 3nm Nanosheet FET Library (Samsung, KNU)
By Technical Paper Link - 13 Aug, 2024 - Comments: 0

A new technical paper titled "Design Technology Co-Optimization and Time-Efficient Verification for Enhanced Pin Accessibility in the Post-3-nm Node" was published by researchers at Samsung Electronics and Kyungpook National University (KNU). Abstract: "As the technology nodes approach 3 nm and beyond, nanosheet FETs (NSFETs) are replacing FinFETs. However, despite the migration of devices ... » read more

Single Vs. Multi-Patterning Advancements For EUV
By Gregory Haley - 20 Jun, 2024 - Comments: 0

As semiconductor devices become more complex, so do the methods for patterning them. Ever-smaller features at each new node require continuous advancements in photolithography techniques and technologies. While the basic lithography process hasn’t changed since the founding of the industry — exposing light through a reticle onto a prepared silicon wafer — the techniques and technology ... » read more

TSMC Reports 4Q2023 Earnings: N2 Still On Track For 2025 Production
By Barry Pangrle - 25 Jan, 2024 - Comments: 0

TSMC reported their 4th quarter and end of year financial numbers for 2023. Year over year, net revenue was down 4.5% to NT$2,161.74 billion, but quarter over quarter revenue was essentially flat at NT$625.52 billion, so it appears that as 3nm is ramping up that revenue is improving. For the fourth quarter, 3nm contributed 15% of TSMC’s total wafer revenue, up from 6% in the third quarter ... » read more

What Will That Chip Cost?
By Brian Bailey - 30 Oct, 2023 - Comments: 1

In the past, analysts, consultants, and many other experts attempted to estimate the cost of a new chip implemented in the latest process technology. They concluded that by the 3nm node, only a few companies would be able to afford them — and by the time they got into the angstrom range, probably nobody would. Much has changed over the past few process nodes. Increasing numbers of startups... » read more

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