Big Trouble At 3nm


As chipmakers begin to ramp up 10nm/7nm technologies in the market, vendors are also gearing up for the development of a next-generation transistor type at 3nm. Some have announced specific plans at 3nm, but the transition to this node is expected to be a long and bumpy one, filled with a slew of technical and cost challenges. For example, the design cost for a 3nm chip could exceed an eye-p... » read more

Chip Dis-Integration


Just because something can be done does not always mean that it should be done. One segment of the semiconductor industry is learning the hard way that continued chip integration has a significant downside. At the same time, another another group has just started to see the benefits of consolidating functionality onto a single substrate. Companies that have been following Moore's Law and hav... » read more

Blog Review: June 13


Synopsys' Taylor Armerding looks at what the flaws in OpenPGP and S/MIME encryption means for the IoT and warns that the problems of patching such devices could lead to an increasing chance of security failures. Cadence's Paul McLellan takes a peek at Imec's roadmap to see what the path to 3nm looks like, how nanosheets fit in, and why design and system technology co-optimization is necessar... » read more

New Transistor Types Vs. Packaging


Plans are being formulated for the rollout of multiple types of gate-all-around FETs and literally dozens of advanced packaging options. The question now is which ones will achieve critical mass, because there aren't enough chips in the world to support all of them profitably. FinFETs, which were first introduced by Intel at 22nm, are running out of steam. While they will survive 10/7nm, and... » read more

Extending The IC Roadmap


An Steegen, executive vice president of semiconductor technology and systems at Imec, sat down with Semiconductor Engineering to discuss IC scaling and chip packaging. Imec is working on next-generation transistors, but it is also developing several new technologies for IC packaging, such as a proprietary silicon bridge, a cooling technology and packaging modules. What follows are excerpts of t... » read more

Quantum Effects At 7/5nm And Beyond


Quantum effects are becoming more pronounced at the most advanced nodes, causing unusual and sometimes unexpected changes in how electronic devices and signals behave. Quantum effects typically occur well behind the curtain for most of the chip industry, baked into a set of design rules developed from foundry data that most companies never see. This explains why foundries and manufacturing e... » read more

The Case For Chiplets


Discussion about chiplets is growing as the cost of developing chips at 10/7nm and beyond passes well beyond the capabilities of many chipmakers. Estimates for developing 5nm chips (the equivalent 3nm for TSMC and Samsung) are well into the hundreds of millions of dollars just for the NRE costs alone. Masks costs will be in the double-digit millions of dollars even with EUV. And that's assum... » read more

Tech Talk: 7/5/3nm Signoff


Anand Raman, director of technical marketing at Helic, explains what's needed to improve confidence in designs at the most advanced process nodes. https://youtu.be/2O2pbMJSta4 » read more

DSA Re-Enters Litho Picture


By Mark LaPedus and Ed Sperling Directed self-assembly (DSA) is moving back onto the patterning radar screen amid ongoing challenges in lithography. Intel continues to have a keen interest in [gettech id="31046" t_name="DSA"], while other chipmakers are taking another hard look at the technology, according to multiple industry sources. DSA isn't like a traditional [getkc id="80" kc_name="... » read more

Why All Nodes Won’t Work


A flood of new nodes, half-nodes and every number in between is creating confusion among chipmakers. While most say it's good to have choices, it's not clear which or how many of those choices are actually good. At issue is which [getkc id="43" kc_name="IP"] will be available for those nodes, how that IP will differ from other nodes in terms of power, performance, area and sensitivity to a v... » read more

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