Backside Power Delivery Gears Up For 2nm Devices

By Laura Peters - 26 Feb, 2024 - Comments: 1

The top three foundries plan to implement backside power delivery as soon as the 2nm node, setting the stage for faster and more efficient switching in chips, reduced routing congestion, and lower noise across multiple metal layers. The benefits of using this approach are significant. By delivering power using slightly fatter, less resistive lines on the backside, rather than inefficient fro... » read more

TSMC Reports 4Q2023 Earnings: N2 Still On Track For 2025 Production

By Barry Pangrle - 25 Jan, 2024 - Comments: 0

TSMC reported their 4th quarter and end of year financial numbers for 2023. Year over year, net revenue was down 4.5% to NT$2,161.74 billion, but quarter over quarter revenue was essentially flat at NT$625.52 billion, so it appears that as 3nm is ramping up that revenue is improving. For the fourth quarter, 3nm contributed 15% of TSMC’s total wafer revenue, up from 6% in the third quarter ... » read more

TSMC Targets N2 Production For 2025

By Barry Pangrle - 02 May, 2023 - Comments: 0

April ended with TSMC’s financial results for the 1st Quarter of 2023 reported on April 20, 2023, and their North American Technology Symposium was held on April 27 at the Santa Clara Convention Center. TSMC’s N3 entered volume production in 4Q 2022 and TSMC’s N2 “nanosheet” technology is on schedule for production in 2025. TSMC’s CEO, C.C. Wei, said during the 1Q conference cal... » read more

What Designers Need To Know About GAA

By Brian Bailey - 13 Apr, 2023 - Comments: 3

While only 12 years old, finFETs are reaching the end of the line. They are being supplanted by gate-all-around (GAA), starting at 3nm [1], which is expected to have a significant impact on how chips are designed. GAAs come in two main flavors today — nanosheets and nanowires. There is much confusion about nanosheets, and the difference between nanosheets and nanowires. The industry still ... » read more

Challenges Grow For CD-SEMs At 5nm And Beyond

By Gregory Haley - 11 Apr, 2023 - Comments: 1

CD-SEM, the workhorse metrology tool used by fabs for process control, is facing big challenges at 5nm and below. Traditionally, CD-SEM imaging has relied on a limited number of image frames for averaging, which is necessary both to maintain throughput speeds and to minimize sample damage from the electron beam itself. As dimensions get smaller, these limitations result in higher levels of n... » read more

Metrology Strategies For 2nm Processes

By Laura Peters - 07 Mar, 2023 - Comments: 3

Metrology and wafer inspection processes are changing to keep up with evolving and new device applications. While fab floors still have plenty of OCD tools, ellipsometers, and CD-SEMs, new systems are taking on the increasingly 3D nature of structures and the new materials they incorporate. For instance, processes like hybrid bonding, 3D NAND flash devices, and nanosheet FETs are pushing the bo... » read more

Highly Dense And Vertically Aligned Sub-5 nm Silicon Nanowires

By Technical Paper Link - 11 Oct, 2022 - Comments: 0

A new technical paper titled "Catalyst-free synthesis of sub-5 nm silicon nanowire arrays with massive lattice contraction and wide bandgap" was published by researchers at Northeastern University, Korea Institute of Science and Technology, Gyeongsang National University and others. "Here, we prepare highly dense and vertically aligned sub-5 nm silicon nanowires with length/diameter aspect r... » read more

Scaling, Advanced Packaging, Or Both

By Ed Sperling - 01 Aug, 2022 - Comments: 0

Chipmakers are facing a growing number of challenges and tradeoffs at the leading edge, where the cost of process shrinks is already exorbitant and rising. While it's theoretically possible to scale digital logic to 10 angstroms (1nm) and below, the likelihood of a planar SoC being developed at that nodes appears increasingly unlikely. This is hardly shocking in an industry that has heard pr... » read more

Extending Copper Interconnects To 2nm

By Laura Peters - 17 Mar, 2022 - Comments: 0

Transistor scaling is reaching a tipping point at 3nm, where nanosheet FETs will likely replace finFETs to meet performance, power, area, and cost (PPAC) goals. A significant architectural change is similarly being evaluated for copper interconnects at 2nm, a move that would reconfigure the way power is delivered to transistors. This approach relies on so-called buried power rails (BPRs) and... » read more

Next-Gen Transistors

By Ed Sperling - 07 Mar, 2022 - Comments: 0

Nanosheets, or more generally, gate-all-around FETs, mark the next big shift in transistor structures at the most advanced nodes. David Fried, vice president of computational products at Lam Research, talks with Semiconductor Engineering about the advantages of using these new transistor types, along with myriad challenges at future nodes, particularly in the area of metrology. » read more

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