Chip Industry Week In Review


Computex in Taiwan: Arm and Nvidia introduced an AI PC platform, RTX Spark, with an Arm-based Grace CPU, Blackwell RTX GPU, and unified memory. Cadence announced a fully autonomous virtual agentic AI design engineer, enabling customers to run dynamic simulations in automated workflows. Intel launched Xeon 6+, its first data-center CPU built on Intel Foundry's 18A process. The company... » read more

Swapping Out Chiplets: I/Os Vs. Compute


Key Takeaways: Companies can save time and money by swapping out a compute, memory, or I/O chiplet to gain technology improvements, while keeping the other dies stable. Chip architects may choose to keep their I/Os stable and swap out compute to move from a 5nm process node to 3nm to achieve performance and power improvements, or swap out memory from LPDDR5X to LPDDR6. Swapping out... » read more

Observability Is Essential For Modern Silicon


Experts At The Table: In-silicon observability — also known as on-die or on-chip visibility — is becoming increasingly important for managing the performance, reliability, and security of today’s high-performance systems. Semiconductor Engineering sat down to discuss this with Andy Nightingale, vice president of product management and marketing at Arteris; Nandan Nayampally, chief commerc... » read more

Wafer-Scale vs. Chiplets: The New War? Part 1


Cerebras’ IPO is a meaningful moment for the semiconductor industry — and not just for the financial implications. Their confidence in their opening price reflects something the industry has effectively acknowledged: incremental chip scaling can no longer keep pace with what AI infrastructure demands. Radical approaches are earning serious consideration and serious capital. Cerebras... » read more

Overcoming Bottlenecks In Data Movement


AI is all about data. There is more data to process, store, and move, and more tradeoffs required to do that efficiently and with enough flexibility to handle changes in future workloads. Nandan Nayampally, chief commercial officer at Baya Systems, talks about networks on chip and networks across chip, what the choke points are for data movement, and where and when data coherency makes sense. » read more

Confusion Grows With More Interconnect Options And Tradeoffs


Key Takeaways: Designers are frequently evaluating 5 or more different interconnects in a single system, each with a distinct purpose. While chip-to-chip (PCIe) and die-to-die (UCIe, BoW) technologies seem to be solving a similar problem, in practice they bring different challenges. PCIe, CXL, NVLink, and UALink are all active in the hyperscaler space, but Ethernet-based technologies... » read more

Foundry Capacity Is Limiting Who Competes At Leading Edge Nodes


Key Takeaways: Leading-edge node access is increasingly reserved for hyperscalers, squeezing smaller chip developers. Chiplets and advanced packaging offer a path forward, but raise cost, complexity, and risk — especially for smaller teams. Chip architecture is now driven as much by capacity, yield, and economics as by technical goals. The benefits of device scaling are sl... » read more

From Standards To Systems: The Chiplet Era On Arm


For three decades, Arm didn’t just participate in industry transformation — it redefined it. From mobile to cloud to automotive, Arm’s architecture and the AMBA ecosystem have become the backbone of scalable compute. Now the industry faces its next structural shift: The era of monolithic SoCs is tapering and giving way to the era of chiplet systems. While complex SoCs are going to b... » read more

NoC Coherency Challenges Balloon With AI SoCs And Chiplets


Key Takeaways Data movement, congestion, and energy efficiency are key determiners of whether compute is usable. Different processors bring various coherency challenges. For example, a cache-coherent NoC for CPUs is expensive and harder to verify than an I/O-coherent NoC for an accelerator. Designers need to balance top-down performance with bottom-up physical engineering to effect... » read more

AI Workloads Are Turning The Data Center Network Into A Combined Memory And Storage Fabric


Recent industry trends, including the release of NVIDIA’s Rubin platform (developer.nvidia.com), point to a growing consensus that AI inference is reshaping data center architecture in a fundamental way. As inference workloads become dominant, the data center network is no longer just a communication layer between servers. It is increasingly part of a distributed memory and storage hierarchy,... » read more

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