Chip Industry Week In Review

By The SE Staff - 17 Jul, 2026 - Comments: 0

Advanced manufacturing, packaging Intel Foundry will invest €5B to expand Intel 3 capacity at its Leixlip, Ireland campus. The company also entered high-volume manufacturing for a subset of Panther Lake processors manufactured on its 18A using ASML’s High-NA EUV technology. UMC delivered the first production wafers for SILITH’s 1.6T silicon photonics platform from its 300mm Singa... » read more

AI Is Rewriting The IP Playbook

By Ann Mutschler - 09 Jul, 2026 - Comments: 0

Key Takeaways: AI is reshaping the entire IP lifecycle, from creation and verification to discovery, licensing, and support. Fast-changing AI models are making flexible IP, robust toolchains, and faster deployment essential. Human expertise remains critical for reviewing, validating, and governing AI-assisted IP development. AI is becoming part of the everyday work o... » read more

Observability Is A Missing Layer In AI-Era Chiplet Design

By Ann Mutschler - 01 Jul, 2026 - Comments: 0

Key Takeaways: In chiplet-based architectures, observability must be designed as a fabric-aligned, cross-die telemetry plane so architects can correlate traffic, latency, congestion, and fault behavior across package boundaries without losing system context. AI can extract value from high-volume silicon telemetry only when the architecture provides consistent instrumentation, near-senso... » read more

I/O Design Challenges Grow In AI Data Centers And HPC Clusters

By Liz Allan - 25 Jun, 2026 - Comments: 0

Key Takeaways: A designer’s choice of I/O connectors and interconnect protocols can be the difference between a massively profitable AI chip and a flop. I/O tradeoffs impact airflow, cooling, rack design, power coming into the rack, and other critical aspects of HPC chip design. Reliability is paramount, so standards must be followed, and I/Os need redundant pins. Other innovations... » read more

Wafer-Scale vs. Chiplets: The New War? Part 2

By Nandan Nayampally - 25 Jun, 2026 - Comments: 0

In Part 1, we looked at the innovations underpinning the Cerebras WSE-3 and why its most significant breakthrough is the elimination of data movement overhead at the architectural level, not better yield management or thermal engineering. Cerebras’ on-wafer fabric is a viable answer to the question being asked by the entire industry: how do you move data fast enough that compute stops wait... » read more

Designing Chips That Can Explain Themselves

By Ann Mutschler - 17 Jun, 2026 - Comments: 1

Key Takeaways: On-die telemetry gives architects a path to replace worst-case design margin with measured silicon behavior, improving PPA without compromising resilience. As monitor density and control-loop speed increase, observability must be architected hierarchically across local hardware response, on-die processing, and fleet-level learning. The real payoff is architectural: str... » read more

Chip Industry Week In Review

By The SE Staff - 12 Jun, 2026 - Comments: 0

Notable deals Cadence and Intel Foundry inked a multi-year agreement to advance design technology co-optimization and create PDKs for Intel Foundry's 14A process. Nvidia and SK hynix announced a multi-year partnership to co-develop memory technology for AI infrastructure and physical AI. Teradyne unveiled an integrated test cell solution with TEL that supports known-good device scree... » read more

Chip Industry Week In Review

By The SE Staff - 05 Jun, 2026 - Comments: 0

Computex in Taiwan: Arm and Nvidia introduced an AI PC platform, RTX Spark, with an Arm-based Grace CPU, Blackwell RTX GPU, and unified memory. Cadence announced a fully autonomous virtual agentic AI design engineer, enabling customers to run dynamic simulations in automated workflows. Intel launched Xeon 6+, its first data-center CPU built on Intel Foundry's 18A process. The company... » read more

Swapping Out Chiplets: I/Os Vs. Compute

By Liz Allan - 28 May, 2026 - Comments: 0

Key Takeaways: Companies can save time and money by swapping out a compute, memory, or I/O chiplet to gain technology improvements, while keeping the other dies stable. Chip architects may choose to keep their I/Os stable and swap out compute to move from a 5nm process node to 3nm to achieve performance and power improvements, or swap out memory from LPDDR5X to LPDDR6. Swapping out... » read more

Observability Is Essential For Modern Silicon

By Ann Mutschler - 28 May, 2026 - Comments: 0

Experts At The Table: In-silicon observability — also known as on-die or on-chip visibility — is becoming increasingly important for managing the performance, reliability, and security of today’s high-performance systems. Semiconductor Engineering sat down to discuss this with Andy Nightingale, vice president of product management and marketing at Arteris; Nandan Nayampally, chief commerc... » read more

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tag: Baya Systems

Chip Industry Week In Review

AI Is Rewriting The IP Playbook

Observability Is A Missing Layer In AI-Era Chiplet Design

I/O Design Challenges Grow In AI Data Centers And HPC Clusters

Wafer-Scale vs. Chiplets: The New War? Part 2

Designing Chips That Can Explain Themselves

Chip Industry Week In Review

Chip Industry Week In Review

Swapping Out Chiplets: I/Os Vs. Compute

Observability Is Essential For Modern Silicon

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