Intel’s expansion; Cadence AI super agent for PCB, advanced packaging; photonics fab wars; earlier Yongin fab; German funding; new CHIPS Act award; HBM standard; Quadric funding; AMS acquisition; earnings; Rapidus teams up.

Fig. 1: Chip concept of a super agent for PCB and advanced packaging. Source: Cadence

Fig. 2: Hideaki Okamoto, director of new generation business development at Mitsubishi Chemical (L.), and Prahald Parthangal, technical director for advanced packaging at Lam Research (R.) deliver keynotes at the SEMI Strategic Materials Conference in San Jose. Source: Semiconductor Engineering
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Fig. 3: A map showing the locations of the NSF Regional Innovation Engines cohorts 1 and 2. Source: NSF
Semiconductor Engineering published the Manufacturing, Packaging and Materials newsletter this week, including:
Plus
Advantest extended its SiConic bench platform into design-for-test engineering, allowing teams to execute, debug, and validate test patterns in a V93000-compatible environment before moving them onto production testers.
Liquid Instruments announced GenInst Studio, which combines agentic AI with reconfigurable hardware to enable engineers to rapidly design and deploy application-specific test instruments in minutes rather than months.
Whalechip successfully deployed ChipAgents‘ AI-powered design platform, enabling its engineering team to rapidly identify critical design issues in a new chip and significantly reduce the time required for root cause analysis.
Infineon Technologies introduced a radiation-hardened GaN high-electron mobility transistor driver designed for satellite and high-reliability space applications.
ZeroPoint, a Swedish memory compression specialist, launched its ZeroStream hardware IP to increase effective memory bandwidth, delivering more tokens per second from AI accelerators.
Chipmind released RTL Canvas, a generative UI for chip design agents, described as a bidirectional contract surface between chip design engineers and AI agents in which engineers sketch architectural intent directly on the RTL diagram.
AI opens the door to exploring a much larger solution space, similar to what high-level synthesis did years ago, but questions persist about the impact of increasing reliance on what is essentially a black-box chip design.
Kandou AI licensed Baya Systems’ WeaveIP fabric and WeaverPro SW platform to help overcome the AI memory wall with copper MIMO technology.
KAIST researchers created a continuous semimetal–semiconductor junction within a single atomically thin PtSe₂ film, reducing the electrical resistance typically introduced where separate metal contacts meet a semiconductor. AFM measurements directly visualized charge transport across the junction, pointing to a potential route to more efficient 2D transistors.
UIUC, Argonne, and UC Colorado researchers created ultra-low-noise, tunable magnetic oscillations in thin-film yttrium iron garnet, enabling up to 40 dB amplification for low-power microwave and spintronic computing.
A CUHK team developed a closed-loop design framework for 3D-ICs, connecting architectural simulation with physical block representation, thermal-aware floor-planning, cache behavior and sustained-frequency modeling.
An ETH Zurich team used “lightweight and practical ML methods to enable adaptive, data-driven control throughout the memory hierarchy,” demonstrating that “integrating adaptive learning into memory subsystems can lead to intelligent, self-optimizing architectures.”
Imec developed a neuromorphic compressive telemetry chip that reduces neural data volumes by more than 10x while preserving signal fidelity.
| More Research | Universities / Institutions |
|---|---|
| Broadband silicon photonic phase shifters driven by gradient optical forces | DTU; EPFL |
| AI-on-Chip Systems: A Cross-Layer Review of Architectures, Interconnects, Design Automation, and Embedded Intelligence | Texas A&M |
| LLM for EDA in Front-End Design: Challenges and Opportunities | TU Munich; TU Ilmenau |
| Ion-Implanted Silicon Nanoregions Enable Ultra-Low-Loss Trimming of Cladded Photonic Integrated Circuits | Heidelberg University; University of Münster |
| Tunable resonant metasurfaces enabled by atomically thin semiconductors | FSU |
| A Thermal-Aware and Comprehensive Design Space Exploration for Chiplet-Based DNN Accelerators | HKUST |
| Exposing and Exploiting Heterogeneous Execution Opportunities for Energy-Efficient Edge LLM Inference | UIUC; AMD |
How Far Left Can You Shift? More steps in the design flow are shifting left, which makes a complicated design process even more complex. This includes early software prototyping, workload mapping, verification, multi-physics integration and IP qualification. Synopsys’ Frank Schirrmeister talks about the increasing number of steps, the potential trouble spots, how reuse and chiplets impact the flow, and what engineers need to know in order to get a working chip out the door and on schedule.
The EU launched Q-PLANET, a €50M European Quantum Chip Stability Pilot Line coordinated by Pasqal to develop industrial-grade chip components for neutral atom quantum computing, sensing, and communication.
The European Space Agency is installing Equal1’s Bell-1 quantum computer, a 6-qubit system, and will research the benefits of hybrid classical-quantum computing for complex Earth observation.
QuiX Quantum launched Carina, a universal photonic quantum computing architecture for commercial deployment, developed for the German Aerospace Center.
Photon Queue won a $500k grant from the New Mexico government and others to establish a local presence and support hiring, lab operations, and quantum device assembly, test, and verification.
New York rolled out an IC manufacturing workforce training tax-credit program to help chip companies offset upskilling and apprenticeship costs, covering up to 75% of eligible training expenses as the state tries to build talent pipelines.
University of Idaho students are creating a virtual-reality cleanroom simulator to give students hands-on semiconductor manufacturing experience without requiring access to a physical cleanroom.
Upcoming webinars are here, including:
Find upcoming chip industry events here, including:
| EVENTS | Date | Location |
|---|---|---|
| ITC India: International Test Conference | July 19 – 21 | Bengaluru |
| The Chips to Systems Conference (DAC) | July 26 – 29 | Long Beach, CA |
| 2026 IEEE International Conference on LLM-Aided Design (ICLAD) | July 30 – 31 | Stanford, CA |
| FMS: Future of Memory and Storage | Aug 4 – 6 | Santa Clara, CA |
| USENIX Security Symposium | Aug 12 – 14 | Baltimore, MD |
| CadenceLIVE India 2026 | Aug 12 | Bengaluru |
| Hot Interconnects | Aug 19 – 21 | Virtual |
| SPIE Optics + Photonics | Aug 23 – 27 | San Diego |
| Hot Chips | Aug 23 – 25 | Palo Alto, CA |
| SEMICON Taiwan | Sept 2 – 4 | Taipei |
| SPIE Photomask Technology + Extreme Ultraviolet Lithography | Sept 8 – 11 | Monterey, CA |
| AI Infra Summit 2026 | Sept 15 – 17 | Santa Clara, CA |
| SEMICON India | Sept 17 – 19 | Delhi, India |
| JEDEC’s Automotive Electronics Forum | Sept 17 | Santa Clara, CA |
| GSA: 2026 U.S. Executive Forum | Sept 22 | Menlo Park, CA |
| TSMC 2026 North America OIP Ecosystem Forum | Sept 23 | Santa Clara, CA |
| IMAPS Microelectronics Symposium 2026 |
Sept 28 – Oct 1 | Everett, Mass |
| Microelectronics UK | Sept 29 – 30 | London |
| Find all events here. |
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