Chip Industry Week In Review

Intel’s expansion; Cadence AI super agent for PCB, advanced packaging; photonics fab wars; earlier Yongin fab; German funding; new CHIPS Act award; HBM standard; Quadric funding; AMS acquisition; earnings; Rapidus teams up.

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Advanced manufacturing, packaging

  • Intel Foundry will invest €5B to expand Intel 3 capacity at its Leixlip, Ireland campus. The company also entered high-volume manufacturing for a subset of Panther Lake processors manufactured on its 18A using ASML’s High-NA EUV technology.
  • UMC delivered the first production wafers for SILITH’s 1.6T silicon photonics platform from its 300mm Singapore fab. The announcement highlights high-volume manufacturing for optical-interconnect manufacturing and gives UMC a production base for its own silicon photonics platform, planned for customer development in 2027.
  • Tower Semiconductor plans a roughly $4B expansion of silicon photonics, silicon-germanium, and advanced-packaging capacity in Japan.
  • TSMC will invest an incremental $100B in advanced semiconductor manufacturing and packaging facilities in Arizona, potentially expanding its footprint to about 12 U.S. fabs and packaging facilities.
  • Samsung plans to begin operations at its first Yongin semiconductor fab by 2029, speeding up the original schedule by one to two years.
  • Shanghai-based startup Yuanjiwei opened a new 8-inch pilot manufacturing line for 2D semiconductors, with plans to use the line for process development and small-volume production, as the company aims for 5nm-equivalent chips without EUV by 2029.

Government interventions

  • The European Commission approved €659M in German subsidies for four new facilities producing silicon carbide epi-wafers, power MOSFETs, semiconductor metrology equipment, and specialized detector chips.
  • The U.S. Commerce Department will provide Bosch CHIPS Act incentives worth up to $225 million to help pay for a $2B conversion of its Roseville, California, facility into a silicon carbide chip fab.
  • India’s government approved ~US$13.2B for Semicon 2.0, covering chip design, equipment and materials, new fabs, advanced packaging, R&D, and workforce development.

Memory

  • JEDEC finalized a new memory standard, JESD330-4, the SPHBM4 standard, which uses a narrower, faster interface to connect HBM4-class memory through organic package substrates rather than silicon interposers..
  • Nanya Technology plans to invest about $16B in its new Taiwan DRAM fab — up from the $9.4B originally planned — with the first phase expected to reach 30,000 wafer starts per month by 2028. The longer-term goal is 45,000 wafers per month.
  • Chinese DRAM maker CXMT’s $8.55B Shanghai IPO was more than 200 times oversubscribed by retail investors.
  • Meanwhile, lawmakers urged the Commerce Department to prohibit U.S. purchases of CXMT and other Chinese memory companies.

New Analysis

Where’s the funding going

Notable deals

  • Rapidus and Cadence are working to integrate Cadence’s InnoStack AI Super Agent into Rapidus’ Raads chip design environment to automate parts of the SoC design flow from architecture through implementation and signoff. The companies aim to better align chip designs with Rapidus’ advanced manufacturing process and make them easier to move into production.
  • Diodes will acquire ElevATE Semiconductor for $250M in cash, adding mixed-signal ICs used primarily in semiconductor automated test equipment.
  • Arteris expanded its partnership with Arm to boost CPU cybersecurity assurance, with Arm further integrating Arteris’ Cycuity Radix technology into its security assurance processes.

Research

  • Imec and Diraq coherently operated and read out an eight-qubit silicon MOS array fabricated in a 300mm CMOS-compatible process, extending foundry-made spin qubits beyond previous one- and two-qubit demonstrations. The result strengthens the case that conventional semiconductor manufacturing can support larger quantum devices.

Innovations

  • DFSX launched its DF1000 high-performance AI accelerator, which combines 3D DRAM near-memory computing with a SW-defined architecture, supporting large-model training and inference.
  • Cadence launched its AuraStack AI Super Agent for PCB and advanced packaging design, delivering up to 2X faster time to market and 15X higher productivity by coordinating domain-specific AI agents across planning, implementation, and multiphysics analysis domains.


Fig. 1: Chip concept of a super agent for PCB and advanced packaging. Source: Cadence

Financials

Around the valley


Fig. 2: Hideaki Okamoto, director of new generation business development at Mitsubishi Chemical (L.), and Prahald Parthangal, technical director for advanced packaging at Lam Research (R.) deliver keynotes at the SEMI Strategic Materials Conference in San Jose. Source: Semiconductor Engineering

Quick links to more news:

Global |In-Depth |Reports and Deals | New Technologies | Security | Vehicles, Batteries | Trending Video | ResearchQuantum | Workforce, Education  Events and Webinars



Global

Americas

  • Siemens EDA expanded its Saskatoon, Canada R&D hub by 10K square feet for a total of 45K square feet.
  • Meta is planning a $50B expansion of its Richland Parish, Louisiana data center to 5GW of compute capacity, with teacher bonuses and local business contracts helping to minimize negative impacts.
  • New York issued a statewide moratorium on new data centers of 50 MW or more, a one-year pause to ensure the state’s residents are not paying for transmission and infrastructure buildouts.
  • The U.S. NSF announced the newest Engines awards to 12 teams across 20 states for critical applications such as semiconductors, energy grid security, critical mineral mining extraction, and advancing quantum computing.

Fig. 3: A map showing the locations of the NSFRegional Innovation Engines cohorts 1 and 2. Source: NSF

Europe

  • The Barcelona Supercomputing Center opened the EuroTPC office as part of the Trillion Parameter Consortium to coordinate researchers, HPC/AI centers, and other players to build open, trustworthy AI for science.
  • Keysight will lead a three‑year development program focused on creating secure, blockchain‑enabled anomaly detection for 5G non‑terrestrial networks.
  • The Chips Joint Undertaking annual activity report 2025 is now available.

Asia

In-Depth

Semiconductor Engineering published the Manufacturing, Packaging and Materials newsletter this week, including:

Plus

 


Reports and Deals

More deals, launches

Fundings, startups

Reports

Opinions


New Technologies

Advantest extended its SiConic bench platform into design-for-test engineering, allowing teams to execute, debug, and validate test patterns in a V93000-compatible environment before moving them onto production testers.

Liquid Instruments announced GenInst Studio, which combines agentic AI with reconfigurable hardware to enable engineers to rapidly design and deploy application-specific test instruments in minutes rather than months.

Whalechip successfully deployed ChipAgents‘ AI-powered design platform, enabling its engineering team to rapidly identify critical design issues in a new chip and significantly reduce the time required for root cause analysis.

Infineon Technologies introduced a radiation-hardened GaN high-electron mobility transistor driver designed for satellite and high-reliability space applications.

ZeroPoint, a Swedish memory compression specialist, launched its ZeroStream hardware IP to increase effective memory bandwidth, delivering more tokens per second from AI accelerators.

Chipmind released RTL Canvas, a generative UI for chip design agents, described as a bidirectional contract surface between chip design engineers and AI agents in which engineers sketch architectural intent directly on the RTL diagram.

AI opens the door to exploring a much larger solution space, similar to what high-level synthesis did years ago, but questions persist about the impact of increasing reliance on what is essentially a black-box chip design.

Kandou AI licensed Baya Systems’ WeaveIP fabric and WeaverPro SW platform to help overcome the AI memory wall with copper MIMO technology.


Research

KAIST researchers created a continuous semimetal–semiconductor junction within a single atomically thin PtSe₂ film, reducing the electrical resistance typically introduced where separate metal contacts meet a semiconductor. AFM measurements directly visualized charge transport across the junction, pointing to a potential route to more efficient 2D transistors.

UIUC, Argonne, and UC Colorado researchers created ultra-low-noise, tunable magnetic oscillations in thin-film yttrium iron garnet, enabling up to 40 dB amplification for low-power microwave and spintronic computing.

A CUHK team developed a closed-loop design framework for 3D-ICs, connecting architectural simulation with physical block representation, thermal-aware floor-planning, cache behavior and sustained-frequency modeling.

An ETH Zurich team used “lightweight and practical ML methods to enable adaptive, data-driven control throughout the memory hierarchy,” demonstrating that “integrating adaptive learning into memory subsystems can lead to intelligent, self-optimizing architectures.”

Imec developed a neuromorphic compressive telemetry chip that reduces neural data volumes by more than 10x while preserving signal fidelity.

More Research Universities / Institutions
Broadband silicon photonic phase shifters driven by gradient optical forces DTU; EPFL
AI-on-Chip Systems: A Cross-Layer Review of Architectures, Interconnects, Design Automation, and Embedded Intelligence Texas A&M
LLM for EDA in Front-End Design: Challenges and Opportunities TU Munich; TU Ilmenau
Ion-Implanted Silicon Nanoregions Enable Ultra-Low-Loss Trimming of Cladded Photonic Integrated Circuits Heidelberg University; University of Münster
Tunable resonant metasurfaces enabled by atomically thin semiconductors FSU
A Thermal-Aware and Comprehensive Design Space Exploration for Chiplet-Based DNN Accelerators HKUST
Exposing and Exploiting Heterogeneous Execution Opportunities for Energy-Efficient Edge LLM Inference UIUC; AMD

Security

Government on security

Hacker karma

  • Two men who livestreamed their hack of Transport for London when they were teenagers were sentenced to five years in prison. The hack disrupted service for months and reportedly cost the transit system £29M.

Alerts, vulnerabilities

Security papers and resources


Vehicles, Batteries

Chips for vehicles

  • Micron signed long-term memory and storage supply agreements with Tier 1 automotive suppliers/partners, including Harman, Visteon, Denso, JOYNEXT, and Hyundai Mobis, to ensure memory supplies for autonomous driving, connectivity, and  SDV platforms.
  • Iridium introduced its positioning, navigation, and timing ASIC, designed to protect GPS- and GNSS-dependent devices from jamming, spoofing, and other growing threats.
  • Nvidia auto head Xinzhou Wu told The Verge’s Decoder podcast that his team still has to fight for its share of the company’s compute resources amid an AI-driven surge in GPU demand.

Autonomous

  • Big screen innovator IMAX will partner with China’s Goer Dynamics to develop an immersive in-vehicle entertainment system for AVs, telling investors that the audio and video displays will help self-driving cars function as “third living spaces.”
  • A Northwestern University team developed a drone capable of becoming nearly invisible while flying. Called the “Phantom Twist,” the drone spins up to 25 times per second, which is too fast for the human eye to see clearly.

EVs, batteries

  • Gigafactory Malaysia will start small-scale production of the country’s first homegrown graphene-enhanced lithium-ion battery for EVs this month.
  • Century Lithium successfully converted lithium carbonate mined from southwest Nevada into lithium metal for battery cells.
  • Battery X Metals reports its patent-pending battery rebalancing technology, which restores usable EV battery capacity through cell balancing rather than battery replacement, is showing good preliminary results.
  • U.S. EV sales in Q2 were down 20.5% compared to last year. While sales improved from Q1 of this year, the quarter marked the third straight year-over-year backslide for U.S. EV sales, according to Cox Automotive analysis.

Vehicle technical papers


How Far Left Can You Shift? More steps in the design flow are shifting left, which makes a complicated design process even more complex. This includes early software prototyping, workload mapping, verification, multi-physics integration and IP qualification. Synopsys’ Frank Schirrmeister talks about the increasing number of steps, the potential trouble spots, how reuse and chiplets impact the flow, and what engineers need to know in order to get a working chip out the door and on schedule.


Quantum

The EU launched Q-PLANET, a €50M European Quantum Chip Stability Pilot Line coordinated by Pasqal to develop industrial-grade chip components for neutral atom quantum computing, sensing, and communication.

The European Space Agency is installing Equal1’s Bell-1 quantum computer, a 6-qubit system, and will research the benefits of hybrid classical-quantum computing for complex Earth observation.

QuiX Quantum launched Carina, a universal photonic quantum computing architecture for commercial deployment, developed for the German Aerospace Center.

Photon Queue won a $500k grant from the New Mexico government and others to establish a local presence and support hiring, lab operations, and quantum device assembly, test, and verification.

Quantum takes


Workforce, Education

New York rolled out an IC manufacturing workforce training tax-credit program to help chip companies offset upskilling and apprenticeship costs, covering up to 75% of eligible training expenses as the state tries to build talent pipelines.

University of Idaho students are creating a virtual-reality cleanroom simulator to give students hands-on semiconductor manufacturing experience without requiring access to a physical cleanroom.


Events and Webinars

Upcoming webinars are here, including:

Find upcoming chip industry events here, including:

EVENTS Date Location
ITC India: International Test Conference July 19 – 21 Bengaluru
The Chips to Systems Conference (DAC) July 26 – 29 Long Beach, CA
2026 IEEE International Conference on LLM-Aided Design (ICLAD) July 30 – 31 Stanford, CA
FMS: Future of Memory and Storage Aug 4 – 6 Santa Clara, CA
USENIX Security Symposium Aug 12 – 14 Baltimore, MD
CadenceLIVE India 2026 Aug 12 Bengaluru
Hot Interconnects Aug 19 – 21 Virtual
SPIE Optics + Photonics Aug 23 – 27 San Diego
Hot Chips Aug 23 – 25 Palo Alto, CA
SEMICON Taiwan Sept 2 – 4 Taipei
SPIE Photomask Technology + Extreme Ultraviolet Lithography Sept 8 – 11 Monterey, CA
AI Infra Summit 2026 Sept 15 – 17 Santa Clara, CA
SEMICON India Sept 17 – 19 Delhi, India
JEDEC’s Automotive Electronics Forum Sept 17 Santa Clara, CA
GSA: 2026 U.S. Executive Forum Sept 22 Menlo Park, CA
TSMC 2026 North America OIP Ecosystem Forum Sept 23 Santa Clara, CA
IMAPS Microelectronics
Symposium 2026
Sept 28 – Oct 1 Everett, Mass
Microelectronics UK Sept 29 – 30 London
Find all events here.



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