Week In Review: Manufacturing, Test


Market research What are the hot chip markets for 2020? IC Insights released its rankings of sales growth rates for each of the 33 IC product categories defined by the World Semiconductor Trade Statistics (WSTS) organization. “After posting the two worst growth rates among all IC product categories in 2019, NAND flash and DRAM are forecast to be among the top three fastest-growing IC segment... » read more

Finding Defects In EUV Masks


Extreme ultraviolet (EUV) lithography is finally in production at advanced nodes, but there are still several challenges with the technology, such as EUV mask defects. Defects are unwanted deviations in chips, which can impact yield and performance. They can crop up during the chip manufacturing process, including the production of a mask or photomask, sometimes called a reticle. Fortunately... » read more

Week In Review: Manufacturing, Test


Chipmakers A fire broke out this week at a joint NAND flash fab between Western Digital (WD) and Kioxia. Kioxia is the former Toshiba NAND flash unit that was recently spun out by the Japanese company. “On Monday, January 6, (morning, January 7 local time) a small fire occurred at one of our joint venture facilities in Yokkaichi, Japan. Local firefighters quickly extinguished the fire, and w... » read more

Week In Review: Manufacturing, Test


Fab tools and materials In a blog, David Haynes, managing director of strategic marketing at Lam Research, talks about the IoT and automotive chip markets, which are fabricated at a wide range of technology nodes. Hoya recently made an unsolicited $1.4 billion bid to acquire NuFlare, a supplier of e-beam mask writers and other equipment. Click here for more information. Hoya makes several p... » read more

Multi-Patterning EUV Vs. High-NA EUV


Foundries are finally in production with EUV lithography at 7nm, but chip customers must now decide whether to implement their next designs using EUV-based multiple patterning at 5nm/3nm or wait for a new single-patterning EUV system at 3nm and beyond. This scenario revolves around ASML’s current extreme ultraviolet (EUV) lithography tool (NXE:3400C) versus a completely new EUV system with... » read more

Making And Protecting Advanced Masks


Semiconductor Engineering sat down to discuss lithography and photomask trends with Bryan Kasprowicz, director of technology and strategy and a distinguished member of the technical staff at Photronics; Thomas Scheruebl, director of strategic business development and product strategy at Zeiss; Noriaki Nakayamada, senior technologist at NuFlare; and Aki Fujimura, chief executive of D2S. What fol... » read more

Week In Review: Manufacturing, Test


Chipmakers The IC industry once had several leading-edge vendors that invested and built new fabs. But over time, the field has narrowed due to soaring costs and a dwindling customer base. In 1994, the share of semiconductor industry capital spending held by the top five companies was 25%, according to IC Insights. This meant that a number of companies invested and built new fabs during the... » read more

Inspecting, Patterning EUV Masks


Semiconductor Engineering sat down to discuss lithography and photomask trends with Bryan Kasprowicz, director of technology and strategy and a distinguished member of the technical staff at Photronics; Thomas Scheruebl, director of strategic business development and product strategy at Zeiss; Noriaki Nakayamada, senior technologist at NuFlare; and Aki Fujimura, chief executive of D2S. What fol... » read more

Week In Review: Manufacturing, Test


Chipmakers The semiconductor capital spending race continues to escalate in the leading-edge logic space. Intel and Samsung have separately announced big capital spending plans in 2019. Intel’s latest CapEx budget is $15.5 billion in 2019, while Samsung’s CapEx is slated for $16.204 billion for the year, according to KeyBanc Capital Markets. Now, TSMC is raising the stakes. TSMC this... » read more

Challenges Grow For Finding Chip Defects


Several equipment makers are developing or ramping up a new class of wafer inspection systems that address the challenges in finding defects in advanced chips. At each node, the feature sizes of the chips are becoming smaller, while the defects are harder to find. Defects are unwanted deviations in chips, which impact yield and performance. The new inspection systems promise to address the c... » read more

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