Rising mask costs, tighter high-NA requirements, and new materials challenges are forcing chipmakers to weigh litho choices against volume, design strategy, and total process cost.
Key Takeaways:
Experts at the table:Semiconductor Engineering sat down to discuss new mask technology challenges with Aki Fujimura, CEO at D2S; Glen Scheid, operations manager at Micron; Harry Levinson, principal lithographer at HJL Lithography; and Germain Fenger, senior director of product management at Synopsys. What follows are excerpts of that conversation. To read part one of this discussion, click here. Part two is here.
L-R: D2S’ Fujimura; Micron’s Scheid; HJL’s Levinson; and Synopsys’ Fenger.
SE: EUV mask writing is time-consuming and expensive. The masks themselves are expensive, the number per device continues to grow, and they get used up faster. How sustainable is the current mask model, and are mask economics beginning to influence design decisions to limit mask consumption?
Fujimura: The number of masks was really exploding, over 100 in some cases, before EUV came in around the 7nm era. That’s actually gotten better now, because EUV can do in single patterning what 193nm requires double or even triple patterning to do. In regions where EUV is not available, companies would have to consider triple or quadruple patterning to go to 7nm or below.
The market has bifurcated. There are many companies that, even if they can buy an EUV machine, choose not to because their business plan for that fab or foundry is to focus on lower cost. There are plenty of electronics you can do at 28nm. You don’t even have to go down to 14nm. The industry has already figured out which applications can afford EUV and which applications don’t need it, and there are many successful fabs that specialize in not doing the leading edge.
For the leading edge, it’s worth it. At a recent GTC, Jensen Huang said he can see $1 trillion worth of GPU orders, up from $500 billion six months ago. That’s what will continue to fund this. What AI did was to provide a proof point that there is a way for software to use tremendous amounts of compute power and do more valuable things — not just faster, but more valuable. That’s why people are buying up nuclear power plants to power AI factories. Compared to that, the cost of EUV is nothing. What’s happening in AI has also translated into our field. We’ve figured out that with more compute power, we can do so much better. And that means there should be more investment in compute, because it’s worth it. It is more expensive, but for segments of the industry where the leading edge is necessary, it is necessary, and it’s the cheapest way to achieve it. The high-NA machine is projected to cost $350 million per unit. That’s extraordinary, but it’s obviously worth it. That’s how the world is going to continue to look, with more and more investment in compute power seen as a necessary cost.
Scheid: If you brought EUV into manufacturing, at some point you made a computation that there’s an ROI benefit, and all the companies doing EUV came out positive on that analysis and made the decision to go forward. But once you have EUV in manufacturing and have built the infrastructure up around it, there’s still a very careful consideration of how much the mask costs when converting layers to EUV or expanding EUV usage. It’s a significant adder to total operational expense. There is some economy of scale. Using the same capital equipment that was purchased specifically for EUV, you can amortize it over more masks. But EUV materials are still very expensive relative to total cost. Even if ROIs are positive today when we’re in a very strong semiconductor market, they might not be tomorrow. We have to keep driving costs down, working closely with our suppliers to understand, as requirements get tighter, how to move forward on technology without increasing costs further.
High-volume products can improve amortization, but cost pressures remain. On mask economics influencing design decisions, it’s not common for masks to be the sole reason for not doing something. However, mask costs are always on the table, and the industry needs to be driving costs down.
Fenger: There’s definitely some consideration of mask cost when comparing different design strategies, but I would caveat that it’s specific to the application. When you’re dealing with a leading-edge HPC product, the cost of a mask is going to be less important than if you’re dealing with a very low-margin product. You make those decisions depending on where in the ecosystem you land.
Another aspect, the cost of EUV curvilinear masks, will become less and less expensive relative to their Manhattan counterparts eventually. Once multi-beam writers become more commonplace, the cost of a curvilinear mask will be only slightly higher than a Manhattan mask. And if you’re going to employ ILT in a mask design, you’re already potentially shrinking the number of masks needed in a given chip, going from multi-patterning to single patterning because you’ve employed ILT. The technology itself can actually reduce the total chip cost by reducing the number of masks needed for a given chip.
Levinson: We’re not at the point where no one is going to use the next node because of mask costs. When you have sufficiently high volumes and can command high prices for your chips, those technologies are going to be made and are being made, and it’s not clear when that would ever stop. But there are other applications where people are not using the most advanced technologies, and mask cost is part of that. I had a client who had a customer making chips for the military. You might think the military has an enormous budget and this shouldn’t be an issue, but when you think about it, there are only 19 B-2 bombers in the world. If you want to upgrade the electronics on the entire fleet, you’re talking about 19 chips plus replacements. So even there, mask costs are an issue.
We also see huge advantages from a power consumption standpoint if you can use application-specific integrated circuits instead of general-purpose chips. We have many reasons to minimize power consumption. We want cell phone batteries to last longer and electric cars to go further. We don’t want to lose the advantages of those application-specific chips by having their prices get too high, because they have a limited market by their very nature. We’re in a mode where we can continue to tolerate increasing costs at the leading edge for higher-priced masks, because there is huge demand for high-bandwidth memory, GPUs, and things like that. At the same time, there’s a huge benefit to continuing to focus on bringing those prices under control, because we grow our market in doing so. All those economic forces are in play right now.
Wise: Mask economics have actually been shaping design decisions for some time. This became particularly evident with the extension of low‑NA EUV into 3x‑nm logic pitches and in DRAM, where cost pressures have driven layouts that combine periphery and array imaging on a single mask. As mask counts and costs increase, designers have increasingly optimized architectures, pitches, and layout strategies to maximize mask reuse and minimize total mask sets, reflecting a clear and growing influence of mask economics on technology choices.
SE: Looking ahead to high-NA EUV, what innovations in materials, patterning techniques, stitching, and other areas will be necessary to support that level of lithography?
Scheid: We’d certainly expect high-NA to enhance any existing mask errors and drive tighter specs across the board, from local CD to EPE, local CDU, and so forth, including higher resolution. All of these things are achievable, and we’re on the right roadmap to drive them. When a technology transition happens, we also expect to see some new specifications. Stitching is one you mentioned. High-NA needs to stitch, and there are a couple of different ways to interlace the masks. We may have some unique challenges with stitching that we need to figure out while this technology is still in development.
Also, on high-NA we expect to see stronger 3D effects, and we have to drive the mask blank materials further — thinner absorbers, possibly different multilayers. There is still a lot to be learned there, but I see an evolution of materials, even including the substrate. At the last BACUS conference, people were talking more about substrates handling higher heat loads. That will also come in with shared applicability to high-power low-NA scanners. These types of changes will continue to drive collaboration between the mask shop, photo teams, and suppliers to push materials and specifications even further.
Fenger: High-NA is going to represent a step function in terms of the requirements for accuracy. Model to reality across all steps will have tighter specs. All the other new EUV effects, such as anamorphic magnification, polarization, and mask 3D have largely been solved by Synopsys. But when we continue to scale and margins shrink, we constantly need improvements in our model accuracy, which is not new. One aspect I want to briefly address is stitching. In mask manufacturing, there’s not a huge impact. But there is an impact in mask review, where you typically emulate a scanner and compare the mask image to the wafer target. In the stitching area, to create the wafer image, you would actually need two masks to do that, and right now there’s no tool that can load two masks and create one wafer image. I see that as a potential gap. It would be ideal if we can avoid it, but I believe it’s something we can’t do. What happens if you have a defect in both masks? How do you qualify whether your repair worked properly?
Levinson: I’m actually a little more optimistic about that than I had been just a short while ago. If one looks at mask 3D effects, they are fundamentally limiting in what you can do, and in a sense, they have to be addressed. That potentially requires new materials and radically increases computational complexity, but we’re starting to get a handle on what’s going on. This year’s SPIE Frits Zernike Award recipient, Andreas Erdmann of the Fraunhofer Institute, gave an invited talk at the recent SPIE Advanced Lithography and Patterning symposium where he actually asked the question: ‘Can you do better with these masks because of the mask 3D effects, rather than despite them?’ He argued that you can use them to your advantage once you start to understand what’s going on, and then tailor the materials accordingly. There’s certainly a lot of work to take those ideas and make them a reality, but it shows that these problems — which I thought were almost intractable a couple of years ago — are now starting to be worked through.
Bruce Smith at Rochester Institute of Technology is going back and looking at the molybdenum-silicon multilayer that we’ve been using for a decade or so, and showing us that there are things we need to be paying closer attention to as we go up to high-NA in particular. There’s a great deal still to do, but I have complete confidence in the smart people in our industry to figure this out. As long as we keep selling lots of products, we have revenues coming in to support all the R&D teams, and these problems will get fixed.
Fujimura: The amazing thing about this community is that for many decades, we’ve had many really hard challenges, and we’ve always overcome them. Sometimes it took more than one node, but we’ve always overcome them. It’s an amazing community, with competitors collaborating and everybody working together to make it happen. I, too, have faith in this community of people.
On the technical side, one of the issues is going to be the size of the SRAFs required on the mask. SRAFs are sub-resolution assist features — very small shapes designed not to print on the wafer, but meant to assist in off-angle illumination and depth of focus. Depth of focus is dictated by the equation, k₂*λ/NA². It’s the square that’s the problem, and depth of focus is known to become an issue with high-NA. That means you have to have SRAFs, and you have to have small SRAFs because larger ones would not print. The question is, how small do we need them? Some people seem to be saying as small as 15nm in mask scale, and 15nm on a mask is not easy. Today’s resists that are fast enough to write the mask quickly cannot really handle 15nm with any degree of certainty. There will be too much variation. I don’t think it’s so much that the multi-beam mask writers are the limit. It’s going to be the resist, and how fast the resist is, that will be the limiting factor. I’m actually trying to figure this out, because we do ILT and we do MPC, and I need to know what problem we need to be able to handle. If it’s 20nm, no problem. If it’s 15nm, it’s at that boundary. There are ways to print very small shapes with advanced multi-beam mask writers using metal oxide resists, and nano-imprint does it all the time. But nano-imprint masks are 1:1-dimension masks, 1/16 the size of the reticle, so write time is 1/16, as well. If you have to write a full reticle, and write it twice because there are two masks for high-N/A, write time matters. That might become an issue.
Scheid: I don’t have a clear answer on resolving features at that scale, either. It’s very evolutionary. People tend to overcome when that wall is reached. We have to have some expectation that beams get faster. The quantity of beams is increasing on each successive generation of multi-beam writers, and the number of parallel beams could potentially go even higher. What is considered a write-time limitation today is often not tomorrow, and if the industry needs to go there, we can find a way.
Wise: High‑NA EUV opens up significant new challenges and opportunities in patterning. One key change is the reduced depth of focus in the resist due to the higher numerical aperture. This directly impacts allowable resist thickness and places tighter requirements on resist profile control and process windows. To support thinner resists, new patterning approaches are required, including the adoption of metal‑oxide–based photoresist materials that offer inherently higher etch selectivity. These materials, in turn, drive the need for novel etch and film technologies that are co‑optimized with the resist for stress management, defectivity control, and selectivity. In addition, the reduced depth of focus inherent to high‑NA systems can be partially mitigated through innovations such as Lam’s 3D‑engineered Aether dry photoresist. Dry resist enables vertical tuning of resist properties, providing an opportunity to adjust absorption and effectively increase the defect‑free depth of focus needed for next‑generation lithography.
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