IC Power Optimization Required, But More Difficult To Achieve


Power optimization is playing an increasingly vital role in chip and chip and system designs, but it's also becoming much harder to achieve as transistor density and system complexity continue to grow. This is especially evident with advanced packages, chiplets, and high-performance chips, all of which are becoming more common in complex designs. Inside data centers, racks of servers are str... » read more

Delivering On Power During HPC Test


The industry’s insatiable need for power in high-performance computing (HPC) is creating problems for test cells, which need to deliver very high currents at very consistent voltage levels through the power delivery network (PDN). In response, ATE, wafer probe, and contactor vendors are introducing some innovative approaches and test procedures that can ensure robust power delivery to ATE pro... » read more

Characterizing and Evaluating A Quantum Processor Unit In A HPC Center


A new technical paper titled "Calibration and Performance Evaluation of a Superconducting Quantum Processor in an HPC Center" was published by researchers at Leibniz Supercomputing Centre, IQM Quantum Computers, and Technical University of Munich. Abstract "As quantum computers mature, they migrate from laboratory environments to HPC centers. This movement enables large-scale deployments,... » read more

The Crucial Role Of High-Performance Computing In 2024: Balancing Cost And Innovation


We live in a world where digital queries run the Information Superhighway and in turn, our lives. This means that the importance of High-Performance Computing (HPC) cannot be overstated. The technology behind this continues to be a cornerstone for advancing our world and improving productivity. To put it another way, can you imagine a day, a week, when you are not querying something? So, let... » read more

What Works Best For Chiplets


The semiconductor industry is preparing for the migration from proprietary chiplet-based systems to a more open chiplet ecosystem, in which chiplets fabricated by different companies of various technologies and device nodes can be integrated in a single package with acceptable yield. To make this work as expected, the chip industry will have to solve a variety of well-documented technical an... » read more

Advanced Packaging Design For Heterogeneous Integration


As device scaling slows down, a key system functional integration technology is emerging: heterogeneous integration (HI). It leverages advanced packaging technology to achieve higher functional density and lower cost per function. With the continuous development of major semiconductor applications such as AI HPC, edge AI and autonomous electrical vehicles, traditional chips are transforming i... » read more

Integrating Energy Efficiency Considerations Into Your Design From The Beginning


Data center networking is responsible for consuming about 1% of the global electricity supply. With the advent and integration of AI into various sectors, the pressure on both hardware and software infrastructures, necessitated by neural networks and extensive language models, is expected to increase significantly. The burgeoning energy consumption by hyperscale data centers emerges as an ur... » read more

Photonics: The Former And Future Solution


Experts at the Table: Semiconductor Engineering sat down to talk about where photonics is in the hype cycle and its secure role in data centers, with James Pond, fellow at Ansys; Gilles Lamant, distinguished engineer at Cadence; and Mitch Heins, business development manager for photonic solutions at Synopsys. What follows are excerpts of that conversation. [L-R]: Ansys’ Pond, Cadence�... » read more

2.5D Integration: Big Chip Or Small PCB?


Defining whether a 2.5D device is a printed circuit board shrunk down to fit into a package, or is a chip that extends beyond the limits of a single die, may seem like hair-splitting semantics, but it can have significant consequences for the overall success of a design. Planar chips always have been limited by size of the reticle, which is about 858mm2. Beyond that, yield issues make the si... » read more

Getting Optimal PPA For HPC & AI Applications With Foundation IP


By Andrew Appleby, Xiaorui Hu, and Bhavana Chaurasia The demand for application-specific system-on-chips (SoCs) for compute applications is ever-increasing. Today, the diversity of requirements means there is a need for a rich set of compute solutions in a wide range of process technologies. The resulting products may have very different but demanding power, performance, and area (PPA) requi... » read more

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