tag: HPC

I/O Design Challenges Grow In AI Data Centers And HPC Clusters
By Liz Allan - 25 Jun, 2026 - Comments: 0

Key Takeaways: A designer’s choice of I/O connectors and interconnect protocols can be the difference between a massively profitable AI chip and a flop. I/O tradeoffs impact airflow, cooling, rack design, power coming into the rack, and other critical aspects of HPC chip design. Reliability is paramount, so standards must be followed, and I/Os need redundant pins. Other innovations... » read more

Cloud HPC For AI: Addressing Latency, Cost, And Scale At The Architectural Level
By Sumit Vishwakarma - 22 Jun, 2026 - Comments: 0

Many organizations assume that moving HPC workloads to the cloud is simply a matter of lifting and shifting on-premises clusters. In practice, that approach often erodes performance, inflates costs, and undermines AI training efficiency. Getting the most out of HPC in the cloud requires a fundamentally different architectural approach — one that minimizes latency, maximizes utilization, an... » read more

Mask Economics Shape High-NA EUV Adoption
By Gregory Haley - 22 Jun, 2026 - Comments: 0

Key Takeaways: Mask costs are not stopping leading-edge scaling, but they increasingly influence design, node, and process choices. High-NA EUV will tighten requirements for CD, EPE, local CDU, mask 3D modeling, stitching, and materials. Reduced depth of focus in High-NA EUV will drive new resist, etch, film, and absorber approaches. Experts at the table: Semiconductor Engin... » read more

Packaging Technologies Redefine AI And HPC Scalability Limits At ECTC 2026
By Lori Scott - 05 Jun, 2026 - Comments: 0

The 2026 IEEE Electronic Components and Technology Conference (ECTC) showcased how advanced packaging can redefine the scalability limits of artificial intelligence (AI) and high-performance computing (HPC). Across 20 technical papers, Intel Foundry engineers and collaborators highlighted breakthrough innovations — from Embedded Multi-die Interconnect Bridge-T (EMIB-T) enabling large multi-d... » read more

Curvilinear Masks Push The Limits Of Inspection And Metrology
By Gregory Haley - 27 May, 2026 - Comments: 0

Key Takeaways: Curvilinear masks require native data flows across design, mask data prep, writing, inspection, and metrology. Inspection is shifting from finding all defects to identifying which mask variations actually print on wafer. High-NA EUV will intensify inspection challenges, particularly for small printable defects and actinic contrast limits. Experts at the table... » read more

Mask Technology Faces A New Set Of Challenges
By Gregory Haley - 21 May, 2026 - Comments: 0

Key Takeaways: Mask inspection and repair remain the critical bottleneck, even as multi-beam writers have reduced mask-writing constraints. Curvilinear masks are becoming viable for critical layers, but qualification, metrology, and inspection standards still lag production needs. Scaling curvilinear requires curvilinear-native data flows, model-based checks, GPU/HPC compute, and les... » read more

Panel-Level Packaging’s Second Wave Meets Engineering Reality
By Gregory Haley - 16 Apr, 2026 - Comments: 0

Key Takeaways Panel-level packaging is arriving not because the engineering is ready, but because wafer-level economics are breaking down. Glass improves the warpage and dimensional stability problems of organic substrates but introduces a different class of failure modes that require materials solutions, not process adjustments. The central challenges of panel-level processing are m... » read more

PCIe 8.0: Enabling The Next Generation Of High Bandwidth Systems
By Lou Ternullo - 09 Apr, 2026 - Comments: 0

As compute architectures evolve to support increasingly data‑intensive workloads, the role of high‑speed I/O has never been more critical. Artificial intelligence, high‑performance computing, hyperscale infrastructure, and advanced networking all depend on moving massive volumes of data efficiently, reliably, and at scale. The PCI‑SIG’s announcement of PCIe 8.0, which targets 256.0... » read more

Early HBM4 Validation Points The Way For Next Generation AI And HPC Systems
By Brett Murdock - 09 Apr, 2026 - Comments: 0

As AI and high‑performance computing systems continue to scale, memory bandwidth has emerged as a primary system‑level constraint. Larger models, higher compute density, and increasingly complex multi‑die designs are driving the need for memory interfaces that can deliver extreme bandwidth while operating within tight power and signal‑integrity margins. High‑Bandwidth Memory (HBM) has... » read more

Advanced Packaging Limits Come Into Focus
By Gregory Haley - 19 Mar, 2026 - Comments: 0

Key Takeaways: Packaging is now a performance variable. Substrate, bonding, and process sequence determine what can be built at scale. Warpage underlies most advanced packaging failures and gets harder to control as package sizes grow. Every proposed solution, such as glass, panel processing, and backside power, solves one problem while creating another. Moore's Law has shif... » read more

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