tag: HPC

AI Buildout Makes HPC Simulation More Challenging
By Ann Mutschler - 11 Dec, 2025 - Comments: 0

Simulations of semiconductors and systems are becoming bigger, more complex, and increasingly necessary, mirroring everything that is happening to the hardware itself — particularly in AI data centers. The move beyond monolithic chips to multi-die assemblies now requires solving some thorny multi-physics challenges, such as thermal and power delivery, which are increasingly difficult to mo... » read more

Designing for 448G: Modulation, DSP, and Channel Trade-offs in High-Speed SerDes
By Synopsys - 10 Dec, 2025 - Comments: 0

Discover practical solutions and engineering insights for deploying 448G SerDes in AI and HPC cluster networks. In this white paper, you’ll learn: The impact of retimed vs. unretimed host architectures on signal integrity and power Key trade-offs between PAM4 and PAM6 modulation Channel design simulations and DSP implications using real-world 448G topologies Equalization stra... » read more

Roadmap for Open-Source Chiplet-Based RISC-V Systems For HPC and AI (ETH Zurich, Univ. of Bologna)
By Technical Paper Link - 25 Nov, 2025 - Comments: 0

A new technical paper titled "Toward Open-Source Chiplets for HPC and AI: Occamy and Beyond" was published by researchers at ETH Zurich and University of Bologna. Abstract: "We present a roadmap for open-source chiplet-based RISC-V systems targeting high-performance computing and artificial intelligence, aiming to close the performance gap to proprietary designs. Starting with Occamy, the f... » read more

From Bottleneck to Breakthrough: Scalable Fabric IP for High- Bandwidth AI and HPC Systems
By Baya Systems - 24 Nov, 2025 - Comments: 0

As compute density and heterogeneity grow rapidly in modern SoCs targeting high-performance computing (HPC) and artificial intelligence (AI) workloads, efficient data movement has emerged as a critical performance and power bottleneck. With increasing core counts, high-speed accelerators, and complex memory hierarchies, traditional bus and crossbar-based interconnects fail to scale, resulting i... » read more

Developing RISC-V Compute Subsystems
By Baya Systems - 29 Oct, 2025 - Comments: 0

As demand grows for scalable, efficient, and customized compute, more companies are turning to RISC-V as the preferred architecture for high-performance computing. Tenstorrent and Baya Systems have designed a compute subsystem combining IP from both companies designed to enable AI and HPC use cases. The solution leverages Tenstorrent’s Ascalon processor and Baya’s advanced interconnect tech... » read more

The Opportunities And Challenges Of FOPLP Technology
By Teck Lee - 23 Oct, 2025 - Comments: 0

Artificial intelligence (AI) has emerged as a major catalyst for innovation and advancement. The growing demand for AI computing power is driving heterogeneous integration toward larger packaging sizes, sparking increased interest in Fan-out Panel Level Package (FOPLP) technology. This article explores ASE’s practices and developments in this area, delving into the technical intricacies and e... » read more

Beyond BPD: Backside Clock and Signal Routing for Sub-3nm (UT Austin, Intel)
By Technical Paper Link - 17 Oct, 2025 - Comments: 0

A new technical paper titled "Beyond Backside Power: Backside Signal Routing as Technology Booster for Standard Cell Scaling" was published by researchers from University of Texas at Austin and Intel. Abstract "Advances in process technology enabling backside metals and contacts offer new Design-Technology Co-Optimization (DTCO) opportunities to further enhance power, performance, and area ... » read more

How 3D-IC Will Change Chip Design
By Ed Sperling - 08 Oct, 2025 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to discuss 3D-IC design challenges and the impact on stacked die on EDA tools and methodologies, with John Ferguson, senior director of product management at Siemens EDA; Mick Posner, senior product group director for chiplet at IP solutions in Cadence's Compute Solutions Group; Mo Faisal of Movellus; Chris Mueth, new opportunities busine... » read more

Identifying Divergences in HW Designs For High Performance Computing Workloads (LBNL et al.)
By Technical Paper Link - 15 Sep, 2025 - Comments: 0

A new technical paper titled "Towards An Approach to Identify Divergences in Hardware Designs for HPC Workloads" was published by Lawrence Berkeley National Lab (LBNL), Foundation for Research and Technology - Hellas and University of Houston Clear Lake. Abstract "Developing efficient hardware accelerators for mathematical kernels used in scientific applications and machine learning has tra... » read more

Rethinking AI Infrastructure: The Rise Of PCIe Switches
By Vanessa Do - 11 Sep, 2025 - Comments: 0

When thinking of AI, images of futuristic robots or self-driving cars may come to mind. What might not come to mind are the unsung hardware component heroes that are quietly enabling such complex systems. Among these, PCI Express (PCIe) switches might seem to be a boring topic to write about, much less read. But here's the twist—they are nothing short of revolutionary when it comes to empower... » read more

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