Wires are treated as a lesser concern, but their neglect is becoming critical at advanced nodes.
Key takeaways:
With every new generation of semiconductor manufacturing process technology there is praise about how much faster transistors are and how much less power they consume. But it is rare that wires — interconnects — get mentioned.
What are typical wire delays? What are the Rs and Cs for each of the layers? Typically, they become worse. Today, wires dominate delays, and in many cases, power.
It all comes down to physics. “Wires have emerged as a major bottleneck, impacting delays, IR drop, power delivery, and congestion,” says Pavan Kumar Ram, application engineering consultant for Siemens EDA. “As device scaling pushes into ever-smaller nodes, we see better-performing transistors, but there is little improvement on the wires that connect them. If we go back to basics, the resistance of a wire is directly proportional to its length and inversely proportional to the cross-sectional area. At advanced geometries, the wire dimensions shrink, and that increases resistance and capacitance as we are packing many things into a very small area, leading to greater signal delays and more pronounced IR drop. This trend is exacerbated by tighter pitches, longer routes, and higher current densities, all of which contribute to thermal issues and reliability concerns.”
This has a significant impact. “Continued advancements on the transistor front, such as finFET to gate-all-around to CFET, are shrinking the dimensions of lower metal layers (M0 to M2) to accommodate design/area scaling,” says Gopi Ranganathan, fellow in the Silicon Solutions Group at Cadence. “M0 resistance has worsened by 100% to 180%, while M2 resistance has worsened by up to 80% as we progress to sub-2nm technologies.”
It also impacts the area. “Wires dominate silicon area,” says Rick Bye, director of product management and marketing for Arteris. “This is not only for the upper-layer metal layers used by the long-distance global interconnect wires in the routing channels between IP blocks, but also for the lower metal layer wires (M0 to ~M6) within the IP blocks themselves.”
Together, this adds up to significant problems. “At advanced nodes, 7nm and below, the interconnect delay has become dominant over gate delay,” says Suhail Saif, director of product management and solutions engineering at Keysight EDA. “The interconnect delay is 60% to even 80% for the smallest-node chips. At 2nm and below, interconnect delay is everything because the transistor is that much faster. Transistor switching has improved 30% to 40% over recent nodes, and that is great. But what about RC delay? The thinner metals are creating more resistance in the wire. The overall RC multiplication is higher. We are talking about saving microseconds or nanoseconds on each transistor optimization, but then wasting even more than that on the interconnect.”
The upshot is that engineering teams are spending more time addressing wire-related issues. “Interconnect delays, especially back-end-of-line (BEOL) M0 to M4, have become a focal point impacting designs,” says Cadence’s Ranganathan. “As a result, the percentage of wire delays in critical timing paths has approached 25% to 30%.”
Designer impacts
The era of just thinking about gates has gone. “Modern design flows increasingly require awareness of wiring constraints, particularly for power and timing closure,” says Siemens’ Ram. “While EDA tools have grown more sophisticated, designers must now collaborate closely with EDA vendors to address wire-related challenges early in the design process. This includes floorplanning for power delivery, managing congestion, and optimizing signal integrity.”
There are multiple dimensions to the problem. “One thought process for solving this interconnect delay is, we have too few interconnects,” says Keysight’s Saif. “Let’s add another layer, and let’s add the potential for more wires so there is less congestion. The wiring requirement has increased as the number of transistors on the same size of chip has increased. One way of creating more wires is to add more layers. But when you add more layers, your packaging limitations are forcing those wires to be of lesser height, so it’s R-squared.”
Another thought is to pack the wires closer together. “That just creates another problem — coupling,” says Matt Commens, director of product management at Synopsys. “This is very important when dealing with higher data rates, and it increases the amount of signal integrity checking that has to be done.”
Routing is critical. “The length of global interconnect wires has a direct impact on latency, power consumption, and area,” says Arteris’ Bye. “Design tools that can minimize wirelength and the number of wires are essential. The availability of sufficient interconnect bandwidth is a key driver of overall system performance. Too few wires will create bottlenecks that constrain performance, but too many wires will unnecessarily increase area.”
Routing is also becoming a lot more complicated. “The complexity and the density of routing is dominating wire capacitance growth,” says Saif. “If you want communication between modules on the upper left corner and the bottom right corner, you have to run wire all the way through. There may be multiple macros that you have to avoid. If there is a macro in between, you either have to go around it, increasing your wire length significantly, or utilize one of the few layers left to go over it. The macro will define if it is consuming 7, 8, or 10 layers out of a possible 13. So now you have only 3 to 5 layers to juggle. All this increases the length of the wire. It’s not line-of-sight. You’re detouring. You are jumping through the layers. Your capacitance is directly proportional to the length of the wire, and capacitance has a double effect. Delays are a factor of RC, but C is also in the equation of power, CV2f.”
Because of this, floorplanning is becoming more critical. “There are floorplanning tools that are intelligent and can generate a lot of interconnect metrics in terms of wire lengths, resistance and capacitance, and power cost,” adds Saif. “Unfortunately, they are not as accurate as we would want, and not as early as we would want. We need to shift left some of the global routing and detailed routing technology to floorplanning. That would increase the accuracy in the floorplanning stage in reporting all these interconnect metrics.”
There are other techniques that can increase the utilization of wires, as well. “Intelligent sharing of wires can help to more efficiently use the interconnect fabric, reducing area and congestion,” says Bye. “Wire sharing requires the use of bandwidth-sharing techniques, such as virtual channels (VCs), along with appropriate quality of service (QoS) mechanisms to ensure that higher-priority data doesn’t get stuck waiting behind lower-priority traffic. NoC IP design tools should offer designers the option to implement virtual channels, particularly in tight, densely packed routing channels, ideally automating the insertion of VCs where necessary and/or beneficial.”
Whichever approach is taken, designers must start thinking in a wire-centric manner. “Designers are now encouraged to consider wire delays, voltage drops, and routing congestion alongside traditional gate-level optimization,” says Ram. “While doing so they need to leverage tightly integrated tools to do faster debug and solving the problem of wire delays and voltage drops.”
Power grids
Power is consumed in a number of ways within a chip, although it usually all gets lumped into the power of the driving transistors. As interconnect length increases, the capacitance of the wire increases, and power is directly proportional to capacitance. It defines the amount of energy that has to be put into or taken out of that capacitor each time it switches logic level. But there is another factor that can be overlooked — coupling capacitance, which is added capacitance when two wires run close to each other. Because of the combined capacitance, dynamic interconnect power has increased to more than 50% of total power.
Some power is consumed in the transistors, but a growing amount is directly associated with driving the signal across the chip. “Interconnect power is increasing percentage-wise,” says Saif. “Absolute wire interconnect power increases, but the percentage increase is even higher, because gate power keeps going down. Tools calculate the power needed to drive the nets in the gate category. If you have to increase your wire length by two, there is twice the capacitance to drive, and the gate has to do more charging and discharging, so more power consumption.”
While many wires carry signals, some are responsible for getting power to where it is needed. “With ever-increasing performance needs, designers must make the power grid more robust to handle higher current and lower IR drop,” says Cadence’s Ranganathan. “They are increasingly utilizing tools to analyze designs with multiple power grids. For example, some strategies include wider metal widths. Some employ continuous-stripe vs. staple methodology for different metal layers to balance available signal routing tracks with power grid needs. Backside power technology also provides relief in this regard, as IR drop improves by up to 40% due to wider lower resistive metal pitches and fewer metals/vias to get from the transistor to the power bumps.”
Backside power delivery is an emerging technology. “In the old days, power was being supplied, along with the signals, on the front side,” says Lang Lin, product management principal at Synopsys. “Now, the power is distributed on the backside, and signals are on the front side of the chip. The power integrity problem is somewhat mitigated, because the signal and power are separated, meaning there’s less coupling between the power noise and the signal, and power also has its own routing spaces. The flip side is that the device has such high current density, and heat is stopped by the backside power like a heat trap. Heat cannot easily go up or down, because the two sides are routed with so many wires, and it will create a lot of problems for heat dissipation.”
It does help with the congestion problem. “It is the global routing wires between the IP blocks, implemented in the upper layers of metal (~M6+) that have the biggest impact on performance and power,” says Bye. “The recently introduced backside power delivery capability helps a little by freeing up some of the upper metal layers that would have been used for power distribution, making more metal layers available for global routing and reducing the impact on area and congestion.”
The dependencies can be tricky to fully understand, however. “By routing power underneath the transistor level, backside power delivery reduces congestion in the top metal layers and improves voltage stability, which can mitigate some of the traditional wiring woes,” says Siemens’ Ram. “However, in some cases this might increase coupling capacitance between signal and clock, as there is no power/ground shielding available for them, and the signal routes can be closer together with power moved to the backside.”
Some of the issues extend beyond silicon. “Wires, especially PCB traces, have become the primary bottleneck in power delivery,” says Eric Pittana, senior director of global marketing and EMEA sales for Empower Semiconductor. “As advanced processors push into multi-kiloamp consumption, wires introduce escalating IR drop, losses, and poorly controlled PDN parasitics. Routing massive currents through dense I/O rings only adds complexity and inefficiency. Backside vertical power delivery is a fundamental shift — moving power beneath the SoC, replacing lossy lateral traces with low-loss vertical vias, and enabling a far more optimized PDN. This changes the design paradigm. Power integrity, current density, and physical layout must now be co-optimized with system architecture. It’s no longer just about gates. It’s about delivering precise, efficient power exactly where and when it’s needed.”
New materials
While transistor technology keeps improving, wires have essentially remained the same. “It’s hard to beat copper,” says Synopsys’ Commens. “It is about as good as it gets, unless you want to do something crazy like use gold, which isn’t going to happen.”
Engineers are looking toward other materials. “All we need is to find a substance that has lower resistivity than the current materials used in chip designing,” says Ram. “Going back to basics — R depends on the material coefficient of ρ (rho) called resistivity of the material. With the advent of gate-all-around, technologists are trying to find materials with lower-k dielectrics to reduce coupling capacitance between signal nets, which are crammed in much smaller spaces than ever before. With reduced dielectric constant, the overall capacitance will reduce and help timing closure, as the crosstalk component that dominates in these lower nodes will reduce with this change.”
There are other possible materials. “Researchers are looking at alternatives like cobalt or ruthenium, or even graphene,” says Saif. “Some of those have a really good potential for reducing resistivity at small geometries, so that will have direct impact on your delay performance and IR drop. But how challenging will it be to integrate that new material onto silicon?”
Another benefit may come from 3D integration, where logic can be stacked vertically. That possibly could shorten average wire lengths by about a factor of 0.7. The problem is that it is a one-time gain, and the problem continues to get worse with each node.
Conclusion
Semiconductor engineers and designers have been focused on metrics like transistor length, gate delays, and gate power. That mindset needs to change to one that also thinks about wire metrics. Average wire length, average wire resistance, and capacitance are needed to provide guidance for good architectures, but this will require new capabilities in floorplanning tools, analysis, and estimation.
There are no easy fixes on the horizon, so this may quickly become a limiter for chip design. “The industry is really good at coming up with creative solutions,” says Saif. “It’s time to focus on solving this interconnect problem, and it will take the entire industry working together to do that.”
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