The Sub-2nm Paradox

By Ed Sperling - 01 Jun, 2026 - Comments: 2

Key Takeaways: Process variation and physics are changing semiconductor design, manufacturing, and economics at 2nm and below. Even though new manufacturing processes are being introduced, it's taking longer for them to mature. The focus for many chip designs is faster data movement and more efficient computing, rather than just relying on more transistors per mm2. At 2nm an... » read more

Gates Add Functionality, But Wires Create Problems

By Brian Bailey - 14 May, 2026 - Comments: 0

Key takeaways: While transistors see continuous improvement, wires keep getting worse because of the smaller geometries and larger chip sizes. There are limited ways to avoid such problems, but the biggest impact will come from floorplanning. Analysis today is not adequate. New developments, such as backside power and 3D integration, provide temporary relief but new materials are a d... » read more

Chiplets 2026: Where Are We Today?

By Barry Pangrle - 24 Feb, 2026 - Comments: 0

Jim Handy of Objective Analysis and Jawad Nasrullah from Palo Alto Electron kicked off last week's Chiplet Summit with predictions about where the chiplet market is headed and why chiplets are needed to accelerate AI. Handy noted that in the 1990s, multi-chip modules (MCMs) led to mid-'90s multi-chip packages (MCPs), and then progressed to NAND flash stacking, stacked die, big chips (e.g., X... » read more

Chiplet Fundamentals For Engineers: eBook

By Bryon Moyer - 02 Feb, 2026 - Comments: 1

Multi-die assemblies are the next phase of Moore's Law, scaling up and out to improve performance and add flexibility into designs. By decomposing SoCs into building blocks, yield improves for the individual dies and overall performance increases because a chip is no longer bound by reticle limits. But this is much harder than it sounds. Chiplets don't just snap together like LEGOs, and so... » read more

Chip Architectures Becoming Much More Complex With Chiplets

By Ed Sperling and Ann Mutschler - 30 Jan, 2025 - Comments: 0

The migration from monolithic SoCs to chiplet-based designs is creating a confusing array of options and tradeoffs for design teams working at the leading edge, and the number of choices is only going to increase as third-party chiplets begin pouring into the market. That hasn't dampened the appetite for chiplets, however, which are deemed essential for future generations of semiconductors f... » read more

Working With Chiplets

By Ed Sperling - 02 Oct, 2024 - Comments: 0

The usual method of migrating to the next process node to cram more features onto a piece of silicon no longer works. It's too expensive, and too limited for most applications. The path forward is now heterogeneous chiplets targeted at specific markets, and while logic will continue to scale, other features are being separated out into chiplets developed using different process technologies. Th... » read more

Legacy Process Nodes Going Strong

By Bryon Moyer - 23 Jul, 2024 - Comments: 1

While all eyes tend to focus on the leading-edge silicon nodes, many mature nodes continue to enjoy robust manufacturing demand. Successive nodes stopped reducing die cost at around the 20nm node. “In the finFET era of processes, esoteric process requirements necessary to move technology forward with each generation have added significant cost and complexity,” explained Andrew Appleby, p... » read more

Who Will Regulate Data Exchanges In Chiplets?

By Ed Sperling - 17 Aug, 2023 - Comments: 0

Scaling is still important when it comes to logic and low power, but it's no longer the main avenue for improving performance. What used to be a single chip, comprised of various IP blocks and components on a single SoC, is giving way to a heterogeneous collection of chiplets — at least for the big chipmakers and system companies at the leading edge. Chiplets are currently the best solutio... » read more

Will CFETs Help The Industry Go Vertical?

By Katherine Derbyshire - 15 Jun, 2023 - Comments: 0

Device scaling is getting much harder at each new process node. Even defining what it means is becoming a challenge. In the past, gate length and metal pitch went down and device density went up. Today, this is much harder for several reasons: • Short channel effects limit gate-length scaling; • Parasitic effects limit device density, and • Metal resistance limits metal pitch. So r... » read more

Memory Evolution Drives Requirements For Design Technology Co-Optimization

By Ricardo Borges - 15 Jul, 2022 - Comments: 0

By Ricardo Borges and Anand Thiruvengadam As new technology nodes have become available, memory has been one of the most aggressive semiconductor applications to adopt advanced process technology. The relentless demand by users of electronic devices for more memory has ensured that investments in new nodes and processes would be quickly repaid by massive sales volumes. As each new node came ... » read more

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tag: device scaling