Will CFETs Help The Industry Go Vertical?

Device scaling is getting much harder at each new process node. Even defining what it means is becoming a challenge.

In the past, gate length and metal pitch went down and device density went up. Today, this is much harder for several reasons:

• Short channel effects limit gate-length scaling;
• Parasitic effects limit device density, and
• Metal resistance limits metal pitch.

So rather than simply shrinking all circuit dimensions, new device architectures must balance these factors to optimize overall circuit performance. As transistors continue to shrink, the minimum separation between them is becoming a critically important obstacle to further increases in device density.

For this reason, nanosheet transistors are attractive because they increase the channel width relative to finFETs, allowing the device to carry more drive current in the same overall footprint. Overall device density, however, is limited by the minimum pMOS/nMOS separation. And while buried power rails help to reduce the overall cell footprint, they leave the p/n separation unchanged.

The forksheet architecture puts an insulating layer between the two channels, reducing this minimum separation. Eventually, though, the available space will be so small that electrons can tunnel through the barrier.

This is where complementary FETs (CFETs) come in. CFETs stack the nMOS devices directly on top of pMOS devices, with an insulating layer between. The lateral p/n separation drops to zero. Signal routing is simplified with both channels in a single vertical structure.

Fig. 1: CFET showing position of nFET and pFET. Source: imec

Of course, the CFET architecture brings a new set of fabrication steps (see figure 1) challenges, too. One approach, the “monolithic” CFET, stacks both p-channels and n-channels in a single nanosheet heterostructure. In work presented at the recent SPIE Advanced Lithography and Packaging Conference, imec’s Hsiao-Hsuan Liu explained that pMOS devices typically are on the bottom, where increased stress helps to reduce the mobility difference between electrons and holes.⁠ [1] The alternative, “sequential” CFET, fabricates the pMOS and nMOS devices on separate wafers, then uses a layer transfer process to combine the two. Neither alternative is easy, but both have advantages relative to the status quo.

Sequential CFETs may perform better, but cost more
The sequential CFET approach seems to have a lot to recommend it. By processing the pMOS and nMOS devices separately, manufacturers gain the ability to optimize them independently. Performance boosters such as strain engineering, and alternative channel materials like SiGe, are easier to incorporate when the two layers are processed separately. On the other hand, using two separate wafers duplicates many FEOL steps. The layer transfer process adds significant cost as well.

Lars Liebmann and colleagues at TEL’s Technology Center in Albany, NY, estimated that monolithic CFETs would cost about the same as a finFET process with buried power rails, while sequential CFETs will increase wafer cost by about an additional 12%. [2] More recent work at imec and SOITEC estimated a 15% overall cost increase for monolithic CFETs relative to nanosheet transistors, and a 30% increase relative to nanosheets for sequential CFETs.⁠ [3] For that reason, many studies have focused on monolithic CFETs exclusively.

While optimizing the two layers separately should give sequential CFETs a performance boost, the need for precise alignment between the two will limit feature dimensions. In particular, features in the metal and gate layers, where the two devices connect, will need to be large enough to accommodate the alignment error. Imec’s Liu expects monolithic CFETs to provide up to 15% more area scaling.

Monolithic CFET fabrication is likely to be less expensive in part because several FEOL steps will only need to be performed once. For instance, a typical integration scheme might build a single Si/SiGe heterostructure — using a process similar to nanosheet transistors — for both the pMOS and nMOS layers. Then, the entire stack is etched in a single step.

Liebmann also estimated that the monolithic process could eliminate an EUV exposure step — a significant savings — by reducing wire congestion in the M0 layer. Monolithic CFET processes also can take advantage of self-alignment, for instance, using SiN spacers alongside the transistor to align subsequent metal depositions. The absence of a layer transfer stepy may make monolithic CFETs may be more suitable for further scaling, as well, due to the absence of a layer transfer step.

Sources and drains at the bottom of a trench
Still, such theoretical cost calculations gloss over substantial process complexity. Transferring a vertical sidewall profile through a thick heterostructure requires careful optimization of the etch conditions. That’s especially true in CFET designs, which insert a SiN insulating layer to separate the two devices.

Geert Mannaert and colleagues at imec took a first step toward a complete CFET process. [4] Rather than attempting to build the full stack, they analyzed a fin with two silicon channels separated by a SiGe layer, focusing on the spacer and source/drain patterning step. After gate etch, they deposited a conformal SiN spacer layer, then etched it to create a recess for the bottom device source/drain.

Even this simplified portion of the full process poses significant challenges (see figure 2).

Fig. 2:  Process flow for creating CFETs. Source: imec

Even this simplified portion of the full process poses significant challenges. The structure to be etched has an 11:1 aspect ratio at a contacted poly pitch of 48nm. The spacer etch should be anisotropic, minimizing lateral SiN spacer consumption. The remaining spacer material should align with the source/drain recess in order to minimize exposure of the gate material during source/drain growth.

The gate oxide hard mask will serve as a stop layer for future CMP steps, so the spacer etch process should avoid eroding it. To maintain electrical isolation, the spacer etch needs high selectivity relative to the isolation oxide. And finally, the profile of the source/drain recess and control of lateral SiGe consumption are critical for the ultimate electrical performance of the device.

In a conventional nanosheet spacer etch process, Mannaert said that the main etch step opens the SiN in the source/drain region and on top of the gate. Tuning plasma conditions to create a carbon cap layer during this step can protect the gate hard mask, but also may impede the later cavity etch. After the main etch, an over-etch step pulls back the spacer along the fin. Removing the SiN exposes the oxide, so a highly selective, highly anisotropic fluorine-based chemistry is typically used for these steps.

Finally, the source/drain cavity etch generally uses chlorine or hydrogen bromide-based plasma. To optimize this process for a CFET process flow, the imec group focused on sidewall profile control in the source/drain cavity etch. Poor passivation can lead to a bowed profile, but an overly thick “polymer” can create an oxygen-rich etch stop layer. Replacing helium with argon increased ion momentum, while tuning the oxygen concentration helped control the thickness of the passivation layer.

As Mannaert emphasized, though, this work was just the beginning. Development of a complete monolithic CFET process will further increase the overall aspect ratio because inserting an insulator is needed between the two devices. This will require even further improvements in etch selectivity.

As with many other process decisions, the needs of a particular device manufacturer may play a role. Cost containment and overall device density may favor monolithic CFETs, while sequential devices may offer superior performance. Whether the simpler sequential CFET process will translate to superior yield is unclear, though, because of the difficulty of transferring a patterned active device layer from one wafer to another.

References

1. Hsiao-Hsuan Liu, et. al., “DTCO of sequential and monolithic CFET SRAM,” Proc. SPIE 12495, DTCO and Computational Patterning II, 124950Z (28 April 2023); doi: 10.1117/12.2657524
2. L. Liebmann, et. al., “CFET Design Options, Challenges, and Opportunities for 3D Integration,” 2021 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 2021, pp. 3.1.1-3.1.4, doi: 10.1109/IEDM19574.2021.9720577.
3. G. Mirabelli, et. al., “Cost analysis of device options and scaling boosters below the A14 technology node,” Proc. SPIE 12495, DTCO and Computational Patterning II, 124951K (28 April 2023); doi: 10.1117/12.2656456
4. G. Mannaert, et. al., “Challenges for spacer and source/drain cavity patterning in CFET devices,” Proc. SPIE 12499, Advanced Etch Technology and Process Integration for Nanopatterning XII, 1249908 (1 May 2023); doi: 10.1117/12.2658073