The Race To Much More Advanced Packaging


Momentum is building for copper hybrid bonding, a technology that could pave the way toward next-generation 2.5D and 3D packages. Foundries, equipment vendors, R&D organizations and others are developing copper hybrid bonding, which is a process that stacks and bonds dies using copper-to-copper interconnects in advanced packages. Still in R&D, hybrid bonding for packaging provides mo... » read more

Yield And Reliability Challenges At 7nm And Below


Layout Design Rules have been scaled very aggressively to enable the 7nm technology node without EUV. As a result, achieving acceptable performance and yield in High Volume Manufacturing (HVM) has become an extremely challenging task. Systematic yield and parametric variabilities have become quite significant. Moreover, due to overlay tolerance requirements and diminishing process windows, reli... » read more

Making Chips At 3nm And Beyond


Select foundries are beginning to ramp up their new 5nm processes with 3nm in R&D. The big question is what comes after that. Work is well underway for the 2nm node and beyond, but there are numerous challenges as well as some uncertainty on the horizon. There already are signs that the foundries have pushed out their 3nm production schedules by a few months due to various technical issu... » read more

Challenges Grow For Finding Chip Defects


Several equipment makers are developing or ramping up a new class of wafer inspection systems that address the challenges in finding defects in advanced chips. At each node, the feature sizes of the chips are becoming smaller, while the defects are harder to find. Defects are unwanted deviations in chips, which impact yield and performance. The new inspection systems promise to address the c... » read more

Test Chips Play Larger Role At Advanced Nodes


Test chips are becoming more widespread and more complex at advanced process nodes as design teams utilize early silicon to diagnose problems prior to production. But this approach also is spurring questions about whether this approach is viable at 7nm and 5nm, due to the rising cost of prototyping advanced technology, such as mask tooling and wafer costs. Semiconductor designers have long b... » read more

New BEOL/MOL Breakthroughs?


Chipmakers are moving ahead with transistor scaling at advanced nodes, but it's becoming more difficult. The industry is struggling to maintain the same timeline for contacts and interconnects, which represent a larger portion of the cost and unwanted resistance in chips at the most advanced nodes. A leading-edge chip consists of three parts—the transistor, contacts and interconnects. The ... » read more

Battling Fab Cycle Times


The shift from planar devices to finFETs enables chipmakers to scale their processes and devices from 16nm/14nm and beyond, but the industry faces several challenges at each node. Cost and technical issues are the obvious challenges. In addition, cycle time—a key but less publicized part of the chip-scaling equation—also is increasing at every turn, creating more angst for chipmakers and... » read more

How Many Nanometers?


What’s the difference between a 10nm and a 7nm chip? That should be a straightforward question. Math, after all, is the only pure science. But as it turns out, the answer is hardly science—even if it is all about numbers. Put in perspective, at 65nm, companies defined the process node by the half pitch of the first metal layer. At 40/45nm, with the cost and difficulty of developing n... » read more

Creating An Accurate FEOL CMP Model


By Ruben Ghulghazaryan, Jeff Wilson, and Ahmed AbouZeid For decades, semiconductor manufacturers have used chemical-mechanical polishing (CMP) as the primary technique for the smoothing and leveling (planarization) of dielectrics and metal layers. CMP modeling allows  design and manufacturing teams to find and fix potential planarization issues before the actual CMP process is applied to a ... » read more

FinFET Front-End-of-Line (FEOL) Process Integration With SEMulator3D


Purely geometric scaling of transistors ended around the 90-nanometer (nm) era. Since then, most power/performance and area/cost improvements have come from structural and material innovations. Silicon-on-Insulator (SOI), first “partially depleted” and more recently “fully depleted” as well as embedded stressors, High-K / Metal-Gate (HKMG) and now FinFETs are examples of technology inno... » read more

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