Author's Latest Posts


2026 ASMC – Building the Core Pillars for AI in Semiconductors


Abstract: This presentation outlines a practical pathway for semiconductor manufacturers to move beyond AI experimentation and achieve scalable, value-driven implementation. As rising process complexity, massive data volumes, and talent constraints make AI a strategic necessity, this presentation highlights why over 70% of AI initiatives stall, primarily due to fragmented data, legacy system... » read more

Features And Benefits Of The SECS/GEM Standard – eBook


Discover how the SEMI E30 SECS/GEM standard empowers smarter, more efficient manufacturing by enabling factories to seamlessly collect equipment data, reduce integration costs, implement advanced process control, and improve overall operational performance. This eBook walks through key GEM capabilities—including collection events, alarms, recipe management, terminal services, and more—to s... » read more

Platform-Led AI Analytics for the Semiconductor Ecosystem


Abstract: Semiconductor manufacturers face a mounting data crisis: modern fabrication facilities generate petabytes of complex, siloed data, yet less than 5% of it is typically used in analytics. Traditional business intelligence tools lack the scalability to handle datasets with millions of parameters, leaving critical yield and quality insights untapped. In this presentation we outline a c... » read more

Addressing Semiconductor Cybersecurity Challenges through Robust Industry Standards and Globally Secure Frameworks


This presentation addresses critical cybersecurity challenges in semiconductor manufacturing by outlining current industry standards (SEMI E187, E188, E191) and their implementation through SMCC workgroups. It identifies key gaps in existing frameworks—particularly the inadequacy of current equipment connectivity standards for distributed collaboration and the scalability challenge of custom ... » read more

Impact of the Gate and Fin Space Variation on Stress Modulation and FinFET Transistor Performance


Device scaling in advanced CMOS nodes is becoming more difficult due to patterning limitations and complex 3-D transistor integration schemes. This also makes the devices more sensitive to patterning variability. The presented study investigates the impact of poly pitch and fin pitch variability on stress-induced performance variation in 7nm FinFET transistors. Variations in critical dimension ... » read more

Revolutionizing Semiconductor Collaboration: The Emergence of AI-Driven Industry Platforms


Demand for advanced computing is robust, driven by AI, cloud technologies, and widespread electrification of the economy. As Moore’s Law slows, the industry is pivoting toward innovative approaches—exploring 3D architectures, chiplets, and sophisticated hybrid packages. Concurrently, the semiconductor landscape is becoming increasingly global, with advanced devices now relying on integratin... » read more

The Growing Need For Collaboration Across The Semiconductor Industry


Abstract: AI-driven collaboration is becoming essential for the semiconductor industry to manage its increasingly complex global supply chain. This new model facilitates real-time data sharing and multi-party orchestration, moving beyond conventional, crisis-driven interactions. By leveraging a secure data infrastructure, automated orchestration, and AI agents, companies can automate busines... » read more

End-to-End Yield Management for Compound Semiconductors Manufacturing


Abstract: Progress in compound semiconductors is hindered by the high level of defectivity of the initial material. Here we take Silicon Carbide manufacturing technology as an example and provide an overview of manufacturing analytics tools and methodologies used to drive yield ramp and capacity expansion. We focus on 2 examples of site-to-site handoff: substrates handoff to IC front-end fab or... » read more

Full Wafer Inspection for Voltage Contrast Systematic Defects Using High-Throughput Point Scan


Abstract: A next generation system and methodology for high-throughput e-beam hot spot inspection is described. Rather than capturing images of each hot spot, just a single pixel centered on the signal node of each hot spot is collected and used to assess if the hot spot is defective or not. This innovation results in a very substantial savings in time per hot spot, and therefore a tremendous ... » read more

Stress-Related Local Layout Effects In FinFET Technology And Device Design Sensitivity


Abstract: "Transistor characteristics in advanced technology nodes are strongly impacted by devices design and process integration choices. Variation in the layout and pattern configuration in close proximity to the device often causes undesirable sensitivities known as Local Layout Effects (LLEs). One of the sensitivities is related to carrier mobility dependence on mechanical stress, modul... » read more

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