Author's Latest Posts


Yield And Reliability Challenges At 7nm And Below


Layout Design Rules have been scaled very aggressively to enable the 7nm technology node without EUV. As a result, achieving acceptable performance and yield in High Volume Manufacturing (HVM) has become an extremely challenging task. Systematic yield and parametric variabilities have become quite significant. Moreover, due to overlay tolerance requirements and diminishing process windows, reli... » read more

Holistic Yield Improvement Methodology


As new products and processes are being introduced into IC manufacturing at an accelerated rate, yield learning and ramping are becoming more challenging due to the increased interaction between the design and process. Compared to random defect caused yield losses, systematic yield loss mechanisms are becoming more important, thus initial yield ramping process becomes more challenging. A “hol... » read more

Circuit-Device Co-design for High Performance Mixed-Signal Technologies


System-on-Chip designs require low cost integration of analog and digital blocks. Often, the analog requirements are not considered sufficiently early in the device design cycle, resulting in devices that are suboptimal for the analog components. This paper presents an innovative methodology for deriving comprehensive device specifications based upon a set of Figure-ofMerit circuits which accou... » read more

Design Compliant Source Mask Optimization (SMO)


Source Mask Optimization (SMO) is required to extend the use of 193 water immersion lithography to the 22nm technology node. Although SMO is being aggressively pushed in volume production the layout design implications of this technology have not been openly discussed. In this paper, the impact of layout design style on simultaneous SMO of Logic and SRAM is studied. In particular the improvemen... » read more

Estimating MOSFET Leakage From Low-Cost, Low-Resolution Fast Parametric Test


A method of estimating the subthershold component of MOSFET off-state current (Ioffs) using low-cost, low-resolution fast parallel parametric test is introduced. This method measures the subthreshold slope and uses it to estimate Ioffs. Measurements of individual transistors show a very good agreement between measured Ioffs and Ioffs estimated using our approach. For a simple pad-efficient tran... » read more