Author's Latest Posts

New Method For BEOL Overlay And Process Margin Characterization
By PDF Solutions - 07 Jun, 2022 - Comments: 0

This paper presents a new method, design for inspection (DFI) to characterize overlay. Using design-assisted voltage contrast measurement, the method enables in-line test and monitoring of process induced OVL and CD variation of backend-of line (BEOL) features with litho-etch-lithoetch (LELE) patterning. While only some of the features of multi-color patterning scheme are chosen to be aligned d... » read more

Novel E-Beam Techniques For Inspection And Monitoring
By PDF Solutions - 09 May, 2022 - Comments: 0

In this paper, we report an advanced e-beam defect inspection tool (eProbe®250) and the Design-for-Inspection™ (DFI) system that has been built and deployed by PDF Solutions down to 4nm FinFET technology nodes. This tool has a very high throughput which allows for in-line inspection of nanometer-level defects in the most advanced technology nodes. We also present eProbe applications for... » read more

Advanced High Throughput e-Beam Inspection With DirectScan
By PDF Solutions - 08 Mar, 2022 - Comments: 0

Optical inspection cannot resolve critical defects at advanced nodes and cannot detect subsurface defects. Especially at 7nm and below, many yield and reliability killer defects are the result of interactions between lithography, etch, and fill. These defects often will have part per billion (PPB) level fail rates. Conventional eBeam tools lack the throughput to measure PPB level fail rates. A ... » read more

Combining Machine Learning With Advanced Outlier Detection To Improve Quality And Lower Cost
By PDF Solutions - 09 Nov, 2020 - Comments: 0

In semiconductor manufacturing, a low defect rate of manufactured integrated circuits is crucial. To minimize outgoing device defectivity, thousands of electrical tests are run, measuring tens of thousands of parameters, with die that are outside of specified parameters considered as fails. However, conventional test techniques often fall short of guaranteeing acceptable quality levels. Given t... » read more

Design And Measurement Requirements For Short Flow Test Arrays To Characterize Emerging Memories
By PDF Solutions - 07 Jul, 2020 - Comments: 0

Emerging non-volatile memories are becoming increasingly attractive for embedded and storage-class applications. Among the development challenges of Back-End integrated memory cells are long learning cycle and high wafer cost. We propose a short-flow based characterization of Memory Arrays using a Cross Point Array approach. A detail analysis of design requirements and testability confirms feas... » read more

IEEE S3S 2019 — Characterization Challenges And Solutions For FDSOI Technologies
By PDF Solutions - 08 Jun, 2020 - Comments: 0

FDSOI technology has been proposed as an alternative device scaling path which offers benefits of tunable, superior electrostatics transistor while maintaining simplicity of planar integration. New device type and integration elements brought up challenges in device and process characterization and monitoring across the whole lifecycle of the technology. This paper presents successful applicati... » read more

Yield And Reliability Challenges At 7nm And Below
By PDF Solutions - 26 May, 2020 - Comments: 0

Layout Design Rules have been scaled very aggressively to enable the 7nm technology node without EUV. As a result, achieving acceptable performance and yield in High Volume Manufacturing (HVM) has become an extremely challenging task. Systematic yield and parametric variabilities have become quite significant. Moreover, due to overlay tolerance requirements and diminishing process windows, reli... » read more

Holistic Yield Improvement Methodology
By PDF Solutions - 06 Apr, 2020 - Comments: 0

As new products and processes are being introduced into IC manufacturing at an accelerated rate, yield learning and ramping are becoming more challenging due to the increased interaction between the design and process. Compared to random defect caused yield losses, systematic yield loss mechanisms are becoming more important, thus initial yield ramping process becomes more challenging. A “hol... » read more

Circuit-Device Co-design for High Performance Mixed-Signal Technologies
By PDF Solutions - 07 Oct, 2019 - Comments: 0

System-on-Chip designs require low cost integration of analog and digital blocks. Often, the analog requirements are not considered sufficiently early in the device design cycle, resulting in devices that are suboptimal for the analog components. This paper presents an innovative methodology for deriving comprehensive device specifications based upon a set of Figure-ofMerit circuits which accou... » read more

Design Compliant Source Mask Optimization (SMO)
By PDF Solutions - 20 Sep, 2018 - Comments: 0

Source Mask Optimization (SMO) is required to extend the use of 193 water immersion lithography to the 22nm technology node. Although SMO is being aggressively pushed in volume production the layout design implications of this technology have not been openly discussed. In this paper, the impact of layout design style on simultaneous SMO of Logic and SRAM is studied. In particular the improvemen... » read more

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