中文 English

The Race To Much More Advanced Packaging

Hybrid bonding opens up a big improvement in die-to-die performance, but getting there is not trivial.

popularity

Momentum is building for copper hybrid bonding, a technology that could pave the way toward next-generation 2.5D and 3D packages.

Foundries, equipment vendors, R&D organizations and others are developing copper hybrid bonding, which is a process that stacks and bonds dies using copper-to-copper interconnects in advanced packages. Still in R&D, hybrid bonding for packaging provides more bandwidth with lower power than the existing methods of stacking and bonding. But hybrid bonding also is more difficult to implement. Plus, the existing technologies may extend further than expected, pushing out the insertion point for hybrid bonding.

Copper hybrid bonding isn’t new. Starting in 2016, CMOS image sensor vendors began shipping products using a wafer-to-wafer hybrid bonding technology. For this, a vendor processes a logic wafer. Then, the vendor processes a separate wafer with the pixels. The two wafers are bonded using fine-pitch copper-to-copper interconnects. The individual chips are diced on the wafer, forming CMOS image sensors.

Hybrid bonding works nearly the same way for advanced packaging, but it’s more complicated. Vendors are working on a different variation called die-to-wafer bonding, where you stack and bond dies on an interposer or other dies. “We are seeing strong industry momentum to develop die-to-wafer hybrid bonding,” said Stephen Hiebert, senior director of marketing at KLA. “Key benefits of die-to-wafer hybrid bonding are its enablement of heterogeneous integration of different-sized chips.”

This version takes advanced packaging to the next level. In one example of today’s advanced packaging, vendors can integrate a multi-die DRAM stack in a package, and connect the dies using the existing interconnect schemes. With hybrid bonding, the DRAM dies are connected using fine-pitch copper-to-copper interconnects, enabling more bandwidth. This approach also could be used for advanced logic on memory stacking and other combinations.

“It has potential for a lot of different applications,” said Guilian Gao, a distinguished engineer at Xperi, in a recent presentation. “Example applications include 3D DRAM, heterogenous integration and chip disaggregation.”

It’s a challenging process, however. Die-to-wafer hybrid bonding requires pristine die, advanced equipment and flawless integration schemes. But if vendors can make it work, the technology could be an appealing option for advanced chip designs.

Traditionally, to advance a design, the industry develops a system-on-a-chip (SoC), where you shrink different functions at each node and pack them onto a monolithic die. But this approach is becoming more complex and expensive at each node. While some will continue to follow this path, many are looking for alternatives. One way to get the benefits of scaling is to assemble complex chips in a traditional advanced package. Advanced packaging using hybrid bonding is yet another option.

GlobalFoundries, Intel, Samsung, TSMC and UMC are all working on copper hybrid bonding for packaging. So are Imec and Leti. In addition, Xperi is developing a version of hybrid bonding. Xperi licenses technology to others.


Fig. 1: 3D integration with hybrid bonding. Source: Xperi

Many packaging options
There are a number of IC package types in the market. One way to segment the packaging market is by interconnect type, which includes wirebond, flip-chip, wafer-level packaging (WLP) and through-silicon vias (TSVs). Interconnects are used to connect one die to another one in packages. TSVs have the highest I/O counts, followed by WLP, flip-chip and wirebond. Hybrid bonding, the interconnect newcomer, has higher densities than TSVs.

Some 75% to 80% of today’s packages are based on wire bonding, according to TechSearch. A wire bonder stitches one chip to another chip or substrate using tiny wires. Wire bonding is used for commodity packages and memory die stacking.

In flip-chip, a sea of larger solder bumps, or tiny copper bumps and pillars, are formed on top of a chip using various process steps. The device is then flipped and mounted on a separate die or board. The bumps land on copper pads, forming an electrical connection. The dies are bonded using a system called a wafer bonder.

WLP, meanwhile, packages the dies while on a wafer. Fan-out is one WLP type. “(Wafer-level packaging) enables us to make smaller two-dimensional connections that redistribute the output of the silicon die to a greater area, enabling higher I/O density, higher bandwidth and higher performance for modern devices,” said Cliff McCold, a research scientist at Veeco, in a presentation at ECTC.

Meanwhile, TSVs are used in high-end 2.5D/3D packages. In 2.5D, dies are stacked on an interposer, which incorporates TSVs. The interposer acts as the bridge between the chips and a board, which provides more I/Os and bandwidth.

There are different versions of 2.5D and 3D packages. High bandwidth memory (HBM), which stacks DRAM dies on each other, is one 3D package type. Stacking logic on logic, or logic on memory, are emerging. “Logic on logic stacking is still not widespread. Logic on memory is something that is coming down the pipeline,” said Ramune Nagisetty, director of process and product integration at Intel.

In packaging, the latest buzzword is chiplets. Chiplets aren’t a packaging type, per se. With chiplets, a chipmaker may have a menu of modular dies, or chiplets, in a library. Customers can mix-and-match the chiplets and connect them using a die-to-die interconnect scheme in a package.

Chiplets could reside in an existing package type or a new architecture. “It’s an architecture methodology,” said Walter Ng, vice president of business development at UMC. “It’s optimizing the silicon solution for the required task. All of those have performance considerations, whether its speed, heat or power. It also has a cost factor, depending on what approach you take.”

For today’s most advanced 2.5D and 3D packages, vendors use existing interconnect schemes and wafer bonders. In these packages, the dies are stacked and connected using copper microbumps and pillars. Based on solder materials, bumps and pillars provide small, fast electrical connections between different devices.

The most advanced microbumps/pillars are tiny structures with 40μm to 36μm pitches. A pitch refers to a given space. A 40μm pitch involves a 25μm copper pillar in size with 15μm spacing.

For fine-pitch requirements, the industry uses thermal compression bonding (TCB). A TCB bonder picks up a die and aligns the bumps to those from another die. It bonds the bumps using force and heat.

TCB, however, is a slow process. On top of that, copper bumps/pillars are approaching their physical limits. Some believe the limit is around 20μm pitches.

Some are trying to extend the bump pitch. Imec is developing a technology that enables 10μm bump pitches using today’s TCB. 7μm and 5μm are in R&D.

Current 40μm bump pitches have enough solder materials to compensate for variations in the flow. “When scaling to 10μm pitch and below, this is no longer the case. In fine-pitch microbumps, the electrical yield and good joint formation is strongly dependent on the accuracy, misalignment and tilt of the TCB tool and amount of the deformation of solder,” said Jaber Derakhshandeh, senior scientist at Imec, in a paper at the recent ECTC conference.

To extend the microbump, Imec has developed a metal spacer process. As before, microbumps are still formed on the die. In Imec’s process, dummy metal microbumps are also formed on the die. Dummy bumps resemble tiny beams that hold up the structure.

“A dummy metal spacer microbump is introduced to 3D die-to-wafer stacking to mitigate tilt error of the TCB tool and to control the solder deformation, so that electrical resistance and joint formation quality of bonding is same for the different locations of the bonded dies,” Derakhshandeh said.

What is hybrid bonding?
At some point, microbumps/pillars and TCB could run out of steam. That’s where copper hybrid bonding fits in. It is expected to be inserted after microbump technology hits the wall, or even before that.

Microbumps aren’t going away anytime soon. Both technologies—microbumps and hybrid bonding—will have a place in the market. This depends on the application.

Hybrid bonding is gaining steam, though. TSMC, the most vocal proponent, is working on a technology called System on Integrated Chip (SoIC). Using hybrid bonding, TSMC’s SoIC technology enables sub-10μm bonding pitches. SoIC is said to have 0.25X the bump-pad pitch over existing schemes. A high-density version enables more than 10X chip-to-chip communication speed with up to nearly 20,000X bandwidth density, and 20X energy efficiency.

Slated for production in 2021, SoIC could enable fine-pitch HBM and SRAM memory cubes, as well as 3D-like chip architectures. Compared to today’s HBMs, “SoIC-integrated DRAM memory cubes can offer higher memory density, bandwidth and power efficiency,” said M.F. Chen, a researcher at TSMC, in a recent paper.

TSMC is developing chip-to-wafer hybrid bonding. Wafer bonding itself isn’t new and has been used in MEMS and other applications for years. There are different types of wafer bonding. “The fabrication and packaging of microelectronic and microelectromechanical systems relies on the bonding of two substrates or wafers,” said Xiao Liu, a senior research chemist at Brewer Science, in a presentation. “In microelectromechanical system (MEMS) fabrication processes, the device wafer will be bonded to another wafer to protect the sensitive MEMS structure. Direct bonding technologies like fusion bonding and anodic bonding or indirect bonding technologies like metal eutectic, thermocompression bonding and adhesive bonding are commonly used methods to serve the microelectronic industry. Using a bonding adhesive as the intermediary between two substrates allows for flexible processing with several advantages.”

Copper hybrid bonding first appeared in 2016, when Sony used the technology for CMOS image sensors. Sony licensed the technology from Ziptronix, now part of Xperi.

For this application, Xperi’s technology is called Direct Bond Interconnect (DBI). DBI is conducted in a traditional fab, and involves a wafer-to-wafer bonding process. In the flow, a wafer is processed and then the metal pads are recessed on the surface. The surface is planarized and then activated.

A separate wafer undergoes a similar process. The wafers are bonded using a two-step process. It’s a dielectric-to-dielectric bond, followed by a metal-to-metal connection.

“Overall, wafer-to-wafer is the method of choice for device manufacturing, where the wafers remain in a front-end fab environment during the whole process flow,” said Thomas Uhrmann, director of business development at EV Group. “In this case, wafer preparation for hybrid bonding has multiple challenges in interface design rules, cleanliness, choice of materials along with activation and alignment. Any particle on the oxide surface introduces a void 100 to 1,000 times larger than the particle size.”

Still, the technology is proven for image sensors. Now, other devices are in the works. “Further devices are planned to follow, such as stacked SRAM to processor dies,” Uhrmann said.

Hybrid bonding for packaging
For advanced chip packaging, the industry is also working on die-to-wafer and die-to-die copper hybrid bonding. This involves stacking a die on a wafer, a die on an interposer, or a die on a die.

This is more difficult than wafer-to-wafer bonding. “For die-to-wafer hybrid bonding, the infrastructure to handle dies without particle adders, as well as the ability to bond dies, becomes a major challenge,” Uhrmann said. “While the interface design and pre-processing for die level can be copied and/or adapted from wafer level, there are multiple challenges arising in die handling. Typically, back-end processes, such as dicing, die handling, and die transport on film frame, have to be adapted to front-end clean levels, allowing high bonding yields on a die level.

“Wafer-to-wafer is working,” Uhrmann said. “When I look at the engineering work and see where the tool development is going (for chip-to-wafer), it’s a very complicated integration task. People like TSMC are pushing the industry. Therefore, we will see it. In production, the safer harbor statement would be somewhere in 2022 or 2023. Potentially, it could be a little bit earlier.”

Hybrid bonding for packaging is different in other ways. Traditionally, IC packaging is conducted at an OSAT or packaging house. In copper hybrid bonding, the process is conducted within a cleanroom in a wafer fab, not an OSAT.

Unlike traditional packaging, which deals with μm-sized defects, hybrid bonding is sensitive to tiny nm-scale defects. A fab-class cleanroom is required to prevent tiny defects from disrupting the process.

Defect control is critical here. “As advanced packaging processes are increasingly complex and the features involved as increasingly smaller, the need for effective process control continues to grow. The cost of failure is high given these processes use expensive known good die,” said Tim Skunes, vice president of R&D at CyberOptics. “Between the components, there are bumps to make the vertical electrical connections. Controlling bump height and coplanarity is vital to ensuring reliable connections between the stacked components.”

Indeed, known good die (KGD) is critical. A KGD is an unpackaged part or a bare die that meets a given specification. Without KGD, the package may suffer from low yields or will fail.

KGD is important for packaging houses. “We receive bare dies and we put them into the package to deliver a product with functionality. People are asking us to provide very high yields,” said Lihong Cao, director of engineering and technical marketing at ASE, at a recent event. “So in regards to known good die, we want to have it fully tested with good functionality. We want it to be 100%.”

Nonetheless, the die-to-wafer hybrid bonding flow is similar to the wafer-to-wafer process. The big difference is the chips are diced and stacked on interposers or other dies using high-speed flip-chip bonders.


Figure 2. Xperi’s die-to-wafer hybrid bonding flow. Source: Xperi

The entire process starts in the fab, where the chips are processed on a wafer using various equipment. That part of the fab is called the front-end-of-the-line (FEOL). In hybrid bonding, two or more wafers are processed during the flow.

Then, the wafers are shipped to a separate part of the fab called the backend-of-the-line (BEOL). Using different equipment, the wafers undergo a single damascene process in the BEOL.

The single damascene process is a mature technology. Basically, an oxide material is deposited on the wafer. Tiny vias are patterned and etched in the oxide material. The vias are filled with copper using a deposition process.

This, in turn, forms copper interconnects or pads on the surface of the wafers. The copper pads are relatively large, measuring on the μm scale. This process is somewhat similar to today’s advanced chip production in fabs. For advanced chips, though, the big difference is that the copper interconnects are measured at the nanoscale.

That’s only the beginning of the process. Here’s where Xperi’s new die-to-wafer copper hybrid bonding process starts. Others use similar or slightly different flows.

The first step in Xperi’s die-to-wafer process is to polish the surface of the wafers using chemical mechanical polishing (CMP). CMP is conducted in a system, which polishes a surface using chemical and mechanical forces.

During the process, the copper pads are slightly recessed on the surface of the wafer. The goal is to obtain a shallow and uniform recess, enabling good yields.

CMP is a difficult process. If the surface is over-polished, the copper pad recess becomes too large. Some pads may not join during the bonding process. If under-polished, copper residue can create electrical shorts.

There is a solution. Xperi has developed 200mm and 300mm CMP capabilities. “CMP technology has progressed significantly in the last decade with innovation around the equipment design, slurry options and in-process monitors to enable repeatable and robust processes with exact control,” said Laura Mirkarimi, vice president of engineering at Xperi.

Then, the wafers undergo a metrology step, which measures and characterizes the surface topography. Atomic force microscopy (AFM) and other tools are used to characterize the surface. AFM uses a tiny probe to enable measurements in structures. In addition, wafer inspection systems are also used.

This is a critical part of the process. “For hybrid bonding, the profile of the wafer surface after damascene pad formation must be measured with sub-nanometer precision to ensure that copper pads meet demanding recess or protrusion requirements,” KLA’s Hiebert said. “The major process challenges of copper hybrid bonding include surface defect control to prevent voids, nanometer-level surface profile control to support robust hybrid bond pad contact, and controlling the alignment of copper pads on the top and bottom die. As hybrid bond pitches get smaller, for example, less than 2μm in wafer-to-wafer flows or less than 10μm in die-to-wafer flows, these surface defect, surface profile, and bond pad alignment challenges become even more significant.”

That may not be enough. At some point during this flow, some may consider a probe step. “Probing directly on copper pads or copper bumps has been traditionally perceived as impossible,” said Amy Leong, senior vice president at FormFactor. “The main concern is how to make stable electrical contact between the probe tips and the bumps.”

For this, FormFactor has developed a MEMS-based probe tip design, dubbed Skate. Combined with a low contact force, the tip gently breaks through the oxidation layer to make electrical contact with the bumps.

More steps
Following the metrology step, the wafers undergo a cleaning and an anneal process. The anneal step is done in batch process with a stack of wafers with the dies on top.

Then, the chips are diced on the wafer using a blade or laser stealth dicing system. This, in turn, creates the individual dies for packaging. The die singulation process is challenging. It can generate particles, contaminants, and edge defects.

“For die-to-wafer hybrid bonding, wafer dicing and die handling add additional sources for particle generation, which must be managed,” KLA’s Hiebert said. “Plasma dicing is under exploration for die-to-wafer hybrid bonding schemes because of its much lower particle contamination levels.”

The bonding step is next. In operation, a flip-chip bonder will pick the die directly from a dicing frame. Then, the system will place the die onto a host wafer or another die. The two structures are immediately bonded at room temperatures. In copper hybrid bonding, chips or wafers are bonded using a dielectric-to-dielectric bond, followed by a metal-to-metal connection.

This process presents some challenges, namely the alignment accuracy of the bonders. In some cases, the alignment accuracies are on the order of several microns. The industry wants sub-μm capabilities.

“While alignment of dies as well as throughput is an engineering challenge, flip chip bonders have already made a tremendous step forward. There is still the challenge of handling dies with the same cleanliness level over the whole population,” EV Group’s Uhrmann said. “Wafer-to-wafer bonding is moving to requirements of less than 100nm overlay and therefore qualifying for advanced nodes. For die-to-wafer, typically there is a dependence between accuracy and throughput, where higher accuracy is traded off by lower population throughput. As the tools have been optimized for backend processes such as solder and thermocompression bonding, a 1µm specification was good enough for a long time. Hybrid die-to-wafer bonding changed equipment designs, triggered by accuracy and equipment cleanliness. The upcoming generation of tools have a specification well below 500nm accuracy.”

The industry is readying the bonders. At ECTC, BE Semiconductor (Besi) presented the first results of a new hybrid chip-to-wafer bonder prototype, with final specification targets of 200nm @ 3 σ, ISO 3 cleanroom environment with 2,000 UPH for 300mm wafer substrates.

“The machine comprises the component wafer table (below the working area), the substrate wafer table, and two mirrored pick-and-place systems (including flipper, cameras, and moving bond heads) working simultaneously on one substrate and a component wafer for double throughput,” said Birgit Brandstätter, funding manager of R&D at Besi, in the paper.

The machine has an input stage, where magazines for substrates (hosts) and component wafers are inserted. These feed into the working area of the machine. The host wafer is transported to the “substrate table.” The component wafer is transported to the “wafer table” located below the “substrate table.” Dies from the component wafer are picked and placed on the substrate wafer.

“A pick-and-place cycle starts with component recognition on the component wafer with the wafer camera. An individual chip is selected, ejected with the ejector needles, picked up with the flipper (either left or right), flipped, and transferred to the pick and place tool (of the corresponding side),” Brandstätter said. “Next, the bond head moves the die over the up-looking (component) camera which determines the exact position of the die on the pick-and-place tool. Hereafter, the bond head moves to the substrate position, and the substrate (downward) camera detects the exact bonding position on the substrate. Sub-micrometer alignment is performed with piezo-actuated drives, and in-situ alignment during accuracy movements is used to further optimize the die position. Finally, the bond head places the die onto the bonding position with the selected bond force and bond delay. The cycle is performed in parallel for left and right side and is repeated until a substrate is fully populated.”

The machine automatically changes substrate and component wafers as required for the production flow, according to the company. To achieve high accuracy, new alignment and optics hardware for fast, robust, and highly accurate alignment are launched, according to the company.

Still, the battle isn’t over. Alignment errors may surface. Defects may crop up. As with all devices and packages, hybrid bonded 2.5D and 3D packages will likely undergo more test and inspection steps. Even then, one bad die could kill the package.

Conclusion
Clearly, hybrid bonding is an enabling technology. It could spawn a new class of products.

But customers will need to weigh the options and dig deeper into the details. It’s not as easy as it sounds.



2 comments

Gretchen Patti says:

Copper hybrid bonding of dies to interposers is no longer in R&D; it’s performed commercially.

Samuel LESKO says:

Die flatness through fine controlled CMP becomes incredibly important. Optical profiler based on White Light Interferometry (WLI) allows full die coverage with µm lateral resolution while retaining sub-nanometer vertical resolution to map out all hot spots, dishing/erosion. It is complementary to AFM in that respect but better scope with need of larger field of view.

Leave a Reply


(Note: This name will be displayed publicly)