Week In Review: Manufacturing, Test


Fab tools/manufacturing Lam Research has accepted Martin Anstice’s resignation as chief executive and a member of the board. Lam has named Tim Archer as president and chief executive effective immediately. Archer, who served as Lam’s president and chief operating officer, has been named to the board. One analyst provided a comment on the situation at Lam. “In our view, Mr. Archer is very... » read more

Week In Review: Design, Low Power


RISC-V Western Digital announced big plans for RISC-V with a new open source RISC-V core, an open standard initiative for cache coherent memory over a network, and an open source RISC-V instruction set simulator. The SweRV Core features a 2-way superscalar design with a 32-bit, 9 stage pipeline core. It has clock speeds of up to 1.8Ghz on a 28mm CMOS process technology and will be used in vari... » read more

Week In Review: Manufacturing, Test


Chipmakers GlobalFoundries has announced that its advanced silicon-germanium (SiGe) offering is available for prototyping on 300mm wafers. GF’s SiGe technology has been shipping on its 200mm production line in Burlington, Vt. The technology, a 90nm SiGe process, is moving to 300mm wafers at GF’s Fab 10 facility in East Fishkill, N.Y. The SiGe technology is called 9HP. “The increasing ... » read more

Week In Review: Design, Low Power


Tools & IP UltraSoC debuted functional safety-focused Lockstep Monitor, a set of configurable IP blocks that are protocol aware and can be used to cross-check outputs, bus transactions, code execution, and register states between two or more redundant systems. It supports all common lockstep / redundancy architectures, including full dual-redundant lockstep, split/lock, master/checker, and... » read more

5 Best Practices For Successfully Managing An ASIC Supply Chain


Managing an end-to-end ASIC supply chain is one of the primary challenges of chip projects. Not only is the process long and complex, but it involves multiple technologies, dependencies and stakeholders. In this paper, we've assembled five best practices to help you translate ASIC specifications into a final product through a smooth supply chain process, including: Avoid costly time-... » read more

Panel Fan-out Ramps, Challenges Remain


After years of R&D, panel-level fan-out packaging is finally beginning to ramp up in the market, at least in limited volumes for a few vendors. However, panel-level fan-out, which is an advanced form of today’s fan-out packaging, still faces several technical and cost challenges to bring this technology into the mainstream or high-volume manufacturing. Moreover, several companies are d... » read more

System-Level Testing – The New Paradigm for Semiconductor Quality Control


Covering the history and trends of system-level test for semiconductors, this solution brief discusses: The increasing complexities of testing advanced semiconductor integrated devices across a span of applications: automotive, mobile computing, wearables, and more; Semiconductor trends driving necessary shifts in testing methodologies including SiP, SoC, 3D finFETs, heterogeneous compo... » read more

ATE Lab To Fab


Shu Li, business development manager at Advantest, zeroes in on the communication gap between engineers on the design side and the manufacturing/test side, why it exists, and what needs to be done to bridge that gap in order to speed up and improve test quality. https://youtu.be/Nd-5_twbJBw     See other tech talk videos here » read more

Using DSA With EUV


James Lamb, deputy CTO for advanced semiconductor manufacturing and corporate technical fellow at Brewer Science, looks at how directed self-assembly can be used to supplement EUV at advanced nodes. https://youtu.be/PItF4egHOxc     See other tech talk videos here » read more

The Week In Review: Manufacturing


Fab tools Applied Materials has launched a suite of products that will enable cobalt metallization schemes for contacts and interconnects in chips at advanced nodes. The products from Applied enable a complete cobalt fill process. The tools include CMP, CVD, PVD and RTP systems. At advanced nodes, cobalt promises to reduce unwanted resistance in the critical parts of a chip. Cobalt is bein... » read more

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