Week In Review: Manufacturing, Test


Fab tools A consortium of 31 companies have launched a new project, called the “Advanced packaging for photonics, optics and electronics for low cost manufacturing in Europe.” The program is referred to as APPLAUSE. With a budget of 34 million euros, the project is being coordinated by ICOS, a division of KLA. “APPLAUSE will focus on advanced optics, photonics and electronics packagin... » read more

Week In Review: Manufacturing, Test


Packaging and test In a major deal that has some implications in the OSAT supply chain, South Korea’s Nepes has taken over Deca Technologies’ wafer-level packaging manufacturing line in the Philippines. In addition, Nepes has also licensed Deca’s M-Series wafer-level packaging technology. This includes fan-in technology as well as wafer- and panel-level fan-out. It also includes an ad... » read more

Week In Review: Manufacturing, Test


Chipmakers United Microelectronics Corp. (UMC) has satisfied all closing conditions for the full acquisition of Mie Fujitsu Semiconductor Ltd. (MIFS), the former 300mm wafer foundry joint venture between UMC and Fujitsu Semiconductor Ltd. (FSL). The completion of the acquisition is scheduled for Oct. 1. In 2014, FSL and UMC agreed for UMC to acquire a 15.9% stake in MIFS from FSL through pr... » read more

Week In Review: Manufacturing, Test


Fab tools The confidence level of extreme ultraviolet (EUV) lithography continues to grow as the technology moves into production, but the EUV mask infrastructure remains a mixed picture, according to new surveys released by the eBeam Initiative. D2S has developed new hardware and software that enables a long-awaited technology--full-chip masks using inverse lithography technology (ILT). ... » read more

Challenges Grow For Finding Chip Defects


Several equipment makers are developing or ramping up a new class of wafer inspection systems that address the challenges in finding defects in advanced chips. At each node, the feature sizes of the chips are becoming smaller, while the defects are harder to find. Defects are unwanted deviations in chips, which impact yield and performance. The new inspection systems promise to address the c... » read more

Using Machine Learning In Fabs


Amid the shift towards more complex chips at advanced nodes, many chipmakers are exploring or turning to advanced forms of machine learning to help solve some big challenges in IC production. A subset of artificial intelligence (AI), machine learning, uses advanced algorithms in systems to recognize patterns in data as well as to learn and make predictions about the information. In the fab, ... » read more

Week In Review: Manufacturing, Test


Chipmakers and OEMs Delphi Technologies is in volume production with a 800 volt silicon carbide (SiC) inverter for next-generation electric and hybrid vehicles. The inverter extends electric vehicle (EV) ranges. It also halves the charging times compared with today's 400 volt systems. In a separate announcement, Delphi Technologies and Cree have announce a partnership to utilize SiC semicon... » read more

Week In Review: Manufacturing, Test


China's DRAM efforts Two memory vendors from China, Tsinghua Unigroup and ChangXin Memory Technology, have disclosed more details about their respective efforts to enter the DRAM arena. As reported, Tsinghua Unigroup wants to enter the DRAM business. Now, the China-based firm has secured land to build a new DRAM fab. The firm recently signed an agreement with the Chongqing government to e... » read more

IP’s Growing Impact On Yield And Reliability


Chipmakers are finding it increasingly difficult to achieve first-pass silicon with design IP sourced internally and from different IP providers, and especially with configurable IP. Utilizing poorly qualified IP and waiting for issues to appear during the design-to-verification phase just before tape-out can pose high risks for design houses and foundries alike in terms of cost and time to... » read more

A Complete System-Level Security Verification Methodology


Hardware is at the root of all digital systems, and security must be considered during the system-on-chip (SoC) design and verification process. Verifying the security of an SoC design is challenging because of time to market pressure and resource constraints. Resources allocated to the already time-consuming task of functional verification must be diverted to security verification, which requi... » read more

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