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Improving Redistribution Layers for Fan-out Packages And SiPs


Redistribution layers (RDLs) are used throughout advanced packaging schemes today including fan-out packages, fan-out chip on substrate approaches, fan-out package-on-package, silicon photonics, and 2.5D/3D integrated approaches. The industry is embracing a variety of fan-out packages especially because they deliver design flexibility, very small footprint, and cost-effective electrical connect... » read more

Week In Review: Manufacturing, Test


Some funding details are now available for the CHIPS Act in the U.S. The Biden Administration plans to spend the money in the following ways: $28 billion to establish domestic production of leading-edge logic and memory chips through grants, subsidized loans or loan guarantees; $10 billion to increase production of current-generation semiconductors and chips, and $11 billion for rese... » read more

Hybrid Bonding Moves Into The Fast Lane


The industry’s unquenchable thirst for I/O density and faster connections between chips, particularly logic and cache memory, is transforming system designs to include 3D architectures, and hybrid bonding has become an essential component in that equation. Hybrid bonding involves die-to-wafer or wafer-to-wafer connection of copper pads that carry power and signals and the surrounding diele... » read more

Fan-Out And Packaging Challenges


Semiconductor Engineering sat down to discuss various IC packaging technologies, wafer-level and panel-level approaches, and the need for new materials with William Chen, a fellow at ASE; Michael Kelly, vice president of advanced packaging development and integration at Amkor; Richard Otte, president and CEO of Promex, the parent company of QP Technologies; Michael Liu, senior director of globa... » read more

Challenges With Chiplets And Packaging


Semiconductor Engineering sat down to discuss IC packaging technology trends, chiplets, shortages and other topics with William Chen, a fellow at ASE; Michael Kelly, vice president of advanced packaging development and integration at Amkor; Richard Otte, president and CEO of Promex, the parent company of QP Technologies; Michael Liu, senior director of global technical marketing at JCET; and Th... » read more

Week In Review: Manufacturing, Test


Chipmakers, OEMs Intel plans to establish foundry capacity at its fab in Ireland. The company has also launched the so-called Intel Foundry Services Accelerator to help automotive chip designers transition from mature to advanced nodes. The company is setting up a new design team and offering both custom and industry-standard intellectual property (IP) to support the needs of automotive custom... » read more

Current And Future Packaging Trends


Semiconductor Engineering sat down to discuss IC packaging technology trends and other topics with William Chen, a fellow at ASE; Michael Kelly, vice president of advanced packaging development and integration at Amkor; Richard Otte, president and CEO of Promex, the parent company of QP Technologies; Michael Liu, senior director of global technical marketing at JCET; and Thomas Uhrmann, directo... » read more

Chipmakers Getting Serious About Integrated Photonics


Integrating photonics into semiconductors is gaining traction, particularly in heterogeneous multi-die packages, as chipmakers search for new ways to overcome power limitations and deal with increasing volumes of data. Power has been a growing concern since the end of Dennard scaling, which happened somewhere around the 90nm node. There are more transistors per mm², and the wires are thinne... » read more

Mobility And 5G Drive Adoption Of New Materials For Power Devices


Electric mobility, renewable energy, and other technology innovations like IoT, 5G, smart manufacturing, and robotics all require reliability, efficiency, and compact power systems, fueling the adoption of silicon carbide (SiC) and gallium nitride (GaN) to support lower voltages in significantly smaller devices. But chip designers must overcome the technological and economical challenges of int... » read more

Blog Review: Jan. 20


Siemens EDA's Harry Foster takes a look at the amount of time IC and ASIC projects spend in verification, changes in the number of engineers on a project, and how engineers are spending their time. Synopsys' Stelios Diamantidis considers the importance of specialized accelerators for AI workloads as both cloud and edge push the PPA limits of current technologies. Cadence's Paul McLellan p... » read more

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