tag: 3D DRAM

DRAM’s Whac‑A‑Mole Security Crisis
By Bryon Moyer - 09 Apr, 2026 - Comments: 0

Key takeaways: Rowhammer remains a DRAM security threat, while Rowpress has increasingly become a related threat. New commands issued by the memory controller can help manage refreshes, but they’re not a perfect solution. A smaller, vertical DRAM cell may eliminate the problem, but it’s years away. Rowhammer has been a persistent DRAM issue across several memory generati... » read more

3D DRAM with CBA Technology (Georgia Tech)
By Technical Paper Link - 16 Mar, 2026 - Comments: 0

A new technical paper, "System-Technology Co-Optimization of Bitline Routing and Bonding Pathways in Monolithic 3D DRAM Architectures," was published by researchers at Georgia Tech. Abstract "3D DRAM has emerged as a promising approach for continued density scaling, but its viability is limited by routing and hybrid bonding constraints to periphery, which may degrade sensing margin, laten... » read more

Making Hybrid Bonding Better
By Laura Peters - 02 Mar, 2026 - Comments: 0

Key Takeaways Fab processes are optimizing for cleanliness, planarity, and high bond quality. Nanotwinned copper and SiCN PVD enable lower anneal and deposition temperatures for HBM. A thin, protective layer helps preserve the Cu/dielectric during aggressive processes. The future of semiconductor manufacturing is no longer dependent just on shrinking features. Instead, chipm... » read more

Rutile TiO2 As A Post-ZrO2 Dielectric Platform for Next-Gen DRAM Capacitors (KIST)
By Technical Paper Link - 07 Feb, 2026 - Comments: 0

Researchers at Korea Institute of Science and Technology (KIST) published "Beyond ZrO2: Rutile TiO2 as the Dielectric Platform for Next-Generation DRAM Capacitors." Abstract "As DRAM technology nodes move into the sub-10 nm regime, capacitor scaling is increasingly constrained by both footprint loss and a hard physical thickness limit for the entire electrode–dielectric–electrode stac... » read more

Overview of ALD-Driven Oxide Semiconductors for High Density, Low Power Memory Architectures (Hanyang Univ., imec)
By Technical Paper Link - 25 Jan, 2026 - Comments: 0

A new technical paper titled "Oxide Semiconductor for Advanced Memory Architectures: Atomic Layer Deposition, Key Requirement and Challenges" was published by researchers a Hanyang University and imec. Abstract "Oxide semiconductors (OSs), introduced by the Hosono group in the early 2000s, have evolved from display backplane materials to promising candidates for advanced memory and logic ... » read more

Interplay Between the Row Hammer Effect and Floating Body Effect in Monolithic 3D Stackable 1T1C DRAM (Georgia Tech)
By Technical Paper Link - 11 Nov, 2025 - Comments: 0

A new technical paper titled "Row Hammer Effect and Floating Body Effect of Monolithic 3D Stackable 1T1C DRAM" was published by researchers at Georgia Institute of Technology. Abstract "Monolithic 3D stackable 1T1C DRAM technology is on the rise, with initial prototypes reported by the industry. This work presents a comprehensive reliability study focusing on the intricate interplay between... » read more

System-HW Co-Design Approach Combines Mono3D DRAM, NMP, and GPU Acceleration (UCSD, Georgia Tech, UIUC, Illinois Tech)
By Technical Paper Link - 14 Oct, 2025 - Comments: 0

A new technical paper titled "Stratum: System-Hardware Co-Design with Tiered Monolithic 3D-Stackable DRAM for Efficient MoE Serving" was published by researchers at UC San Diego, Georgia Tech, University of Illinois Urbana-Champaign and Illinois Institute of Technology. Abstract "As Large Language Models (LLMs) continue to evolve, Mixture of Experts (MoE) architecture has emerged as a preva... » read more

Epitaxial Growth Of Up To 120 Si/SiGe Bilayers In View of 3D DRAM Applications (imec, Ghent Univ.)
By Technical Paper Link - 05 Aug, 2025 - Comments: 0

A new technical paper titled "Epitaxial growth of up to 120× {Si0.8Ge0.2/Si} bilayers in view of three dimensional dynamic random access memory applications" was published by researchers at imec and Ghent University. Abstract "Epitaxially grown Si/Si1−xGex multi-stacks with ≥100 bilayers (≥200 sublayers) are being considered for three dimensionally vertically stacked dynamic rando... » read more

Baby Steps Toward 3D DRAM
By Bryon Moyer - 17 Dec, 2024 - Comments: 0

Flash memory has made incredible capacity strides thanks to monolithic 3D processing enabled by the stacking of more than 200 layers, which is on its way to 1.000 layers in future generations.[1] But the equally important DRAM has achieved a similar manufacturable 3D architecture. The need for a sufficiently large means of storing charge — such as a capacitor — has proved elusive. Severa... » read more

Is In-Memory Compute Still Alive?
By Bryon Moyer - 12 Dec, 2024 - Comments: 1

In-memory computing (IMC) has had a rough go, with the most visible attempt at commercialization falling short. And while some companies have pivoted to digital and others have outright abandoned the technology, developers are still trying to make analog IMC a success. There is disagreement regarding the benefits of IMC (also called compute-in-memory, or CIM). Some say it’s all about reduc... » read more

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