3D Metrology Meets Its Match In 3D Chips And Packages

Next-generation tools take on precision challenges in three dimensions.


The pace of innovation in 3D device structures and packages is accelerating rapidly, driving the need for precise measurement and control of feature height to ensure these devices are reliable and perform as expected throughout their lifetimes.

Expansion along the z axis is already well underway. One need look no further than the staircase-like 3D NAND stacks that rise like skyscrapers to pack hundreds of memory cells cost effectively, the recent introduction of gate-all-around transistors, and soon, 3D DRAM. Makers of optical CD (OCD) and CD-SEMs are advancing capabilities in the vertical direction to characterize GAA transistors and increasingly taller features in 3D NAND. In the back end, 3D packaging is emerging as the best way to tightly integrate chiplets, which require high-bandwidth communication and lower power consumption in a smaller footprint.

Capturing minute changes in the profile and shape of very deep features inline, without slowing down fab production, is possibly the most challenging feat for CD metrology. At the same time, reproducible etch depths are critical to transistor performance. This includes the recess depth of replacement metal gates in GAA-FETs, as well as in next-generation complementary FETs (CFETs).

The workhorse technology for deep features is scatterometry, using optical or near-infrared wavelengths of light to measure re-entrant profiles as deep as 10 microns. A beam of visible or IR light irradiates the chip, and the change in the spectrum of the reflected light is used to determine the shape of the circuit pattern in the illuminated area. But growing complexity of the stacks makes it more difficult to rely solely on scatterometry.

Additional interactions in advanced nodes are happening also in the 3rd dimension, vertically and diagonally, due to new device architectures and integration schemes. And with each process node, the process window shrinks. “Several things are happening,” said Tomasz Brozek, technical fellow at PDF Solutions. “The process windows and tolerances are shrinking, so people are self-aligning the structures, which began with Intel at the 22nm node with self-alignment of the contact to gate. So we’re seeing increasing adoption of self-alignment schemes, because they are easier to manufacture and that buys you margin and yield.

But tight overlay control, the lining up of overlapping features like tall metal contact to a specific word line pad is also essential in 3D NAND. “NAND stacks can become stressed, which causes bowing of the wafer, so even with exactly vertical etching processes, the channel hole can be not perpendicular to the wafer but slightly off, which can cause a short to the neighboring word line pad and connection to the wrong word line,” adds Brozek.

In addition to OCD, CD-SEMs play an essential role in imaging and controlling narrow and deep features using electron beams. Imaging deeply buried structures requires specific configurations of scanning electron microscope. The latest high-voltage SEMs, with accelerating voltages in the 20 to 45kV range, can penetrate the film surfaces, and produce backscattered electrons in response to changing topology. Together with Monte Carlo simulation, sufficient image contrast between buried features can be realized.

In front-end processes, CD-SEM and OCD/IRCD measurements are most commonly used in fabs, though various X-ray techniques also are gaining application-specific use. “Higher resolution XRD and XRR are well-established techniques for thin film analysis in R&D. But now, with the change to gate-all-around, there is this increased need for metrology,” said Juliette van der Meer, product marketing manager at Bruker. “We launched a new tool with increased source power and a better detector to keep up with those needs in high volume manufacturing.”

Examining 3D structures
In advanced logic devices, novel gate-all-around devices using nanosheet or forksheet channels surrounded by gates, are driving three-dimensional metrology. At the same time, 28nm 3D NAND and upcoming 3D DRAM will benefit from 3D metrology that reveals feature height.

Patterning, etching, filling, and CMP processes are needed to produce the next-generation structures that will become the transistors, capacitors, or interconnects in advanced devices. A critical aspect of patterning is producing structures with identical feature shape and dimensions across the patterned area, across the wafer, wafer-to-wafer, and lot-to-lot in high-volume production.

Beginning at around 2010 with the first 3D devices, scatterometry solidified its place in the process control loop because it can measure structure dimensions that are invisible to top-down approaches, such as re-entrant features and gratings with profiles larger than 90 degrees. Scatterometry, which combines spectroscopic ellipsometry and reflectometry, is so called because scattered light from a periodic array is used to determine feature dimensions and shape. And in recent years, companies gained a further advantage by shifting the operating range of scatterometry tools to the mid-infrared wavelengths.

This change enabled better contrast between materials with similar optical properties, such as the dielectrics, silicon dioxide, and silicon nitride. “For decades, OCD measurements operated in the UV, visible, and near-infrared part of the spectrum, at 3,000, 4,000 and 5,000 nanometers, or 3-5 micron. But when you go to 6 micron, and especially 7.5 micron and above, you start to get higher differentiation between adjacent materials,” said Nick Keller, director of applications development at Onto Innovation. “And it is important for us to measure the lateral silicon nitride recess in a 3D NAND channel structure because it has a profound effect on device performance.”

IRCD achieves a spectral response between the silicon nitride recess and the channel hole CD (see figure 1). The silicon nitride lateral recess is filled with a self-aligned charge trap layer that improves data retention and reliability by eliminating lateral charge migration.

Fig. 1: Differentiation between the channel hole CD and silicon nitride recess CD using IRCD. Source: Onto Innovation

Sensitivity in OCD and IRCD depends on factors such as the difference in refractive index of adjacent materials and the volume of material being imaged. “In general, sensitivity is going to come down to the overall volume per unit area of the sample material times the refractive index difference between that material versus the refractive index and material that is next to it. The best contrast that you can get is going to be metal-to-air and silicon-to-air,” said Keller.

In DRAM, the most challenging structure to measure occurs at the capacitor etch. “Customers usually want to know the full profile and the z dimension of the capacitor because it has impact on the device performance. That’s challenging because it’s a high aspect ratio etch through dielectrics, and you need to get multiple parameters. Anytime you have a high-aspect-ratio etch through dielectrics, you’re automatically going to have lower sensitivity just because it’s the dielectric-to-air interface. In this case, there are also low-sensitivity parameters at the bottom of the capacitor, where they actually want to recess the landing a certain amount. That’s a low-sensitivity parameter because it’s very low-volume. So that’s also a challenge.”

In addition to modeling and Mueller matrix calculations, signal response sensitivity is enhanced by machine learning.

“The really big enabler there is utilizing the Mueller matrix together with model-guided machine learning,” said Keller. “The machine learning not only speeds up time to solution, but it enables customers to implement IRCD during pathfinding and test runs when they’re tweaking the process so much. You still have to do the calculations, but the greatest benefit is it actually picks out the most differentiated parts of your signal response and accentuates those responses to achieve the absolute accuracy faster.”

It’s important to keep in mind that scatterometry is an indirect metrology method, so correlation with reference values is essential, often using destructive methods such as cross-sectional SEM or transmission electron microscopy (TEM). “For DRAM and advanced logic, TEM is the gold standard. But for 3D NAND, because of the high aspect ratio and the overall dimensions, which can be 10 micron or higher, TEM is very difficult. So sometimes it will be SEM, and sometimes it will be some other hybrid methods of reference,” said Keller.

Progress in CD-SEMs and X-ray metrology
CD-SEM, in contrast, is traditionally referred to as a top-down measurement method, where secondary electrons generated at feature edges enable x and y measurement of critical dimensions with high precision and accuracy. So it may seem counterintuitive, but under the right operating conditions, CD-SEMs also are capable of feature depth measurements.

At the other extreme, CD-SEMs are dialing down the acceleration voltage for leading-edge chips that require EUV lithography (13.5nm wavelength). Obtaining high resolution, along with balancing the height/width ratio so the photoresist doesn’t collapse, dictates the use of a very thin (30nm) photoresist to form the latent image for line, space, and trench patterns.

Unfortunately, the energy of CD-SEMs at everyday voltages of 500V tends to damage and shrink the EUV photoresist masks. So to minimize this shrinkage, some of the latest CD-SEMs dial down the acceleration voltage level to about 100V and use multi-point measurements to reduce the shrinkage to acceptable levels (see figure 2).

Fig. 2: Photoresist shrinkage of EUV photoresist as a function of landing energy (above) and resulting SEM images. Source: Hitachi High-Tech

With the move to 3D structures, high-voltage CD-SEMs were introduced to measure height dimensions in very deep structures. To image trench bottoms, the detector captures the signal from back-scattered electrons (rather than secondary electrons) to measure pattern depth in the z direction.

Another change that CD-SEM manufacturers have made helps improve the resolution of the tool with respect to feature size it is measuring. Uncertainty in CD-SEM measurements is ruled by the spot size of the electron beam, which is 1nm. [1] It was 1nm when feature sizes were 20nm, and it’s still 1nm with some critical features approaching 15nm. As a percentage, uncertainty in CD-SEM images is growing as features shrink. One way to overcome this uncertainty is to increase the spot size of the e-beam and increase the field of view (FOV), which processes more data per beam for so-called “massive metrology averaging” without decreasing throughput. ASML, Hitachi High Tech, and others offer these massive metrology tools.

X-ray fluorescence, meanwhile, is emerging as a potential inline metrology tool for measuring the cavity formed after SiGe selective etching in the SiGe/Si superlattice for gate-all-around transistors. Bruker and imec recently showed that micro hard XRF provided cavity depth values in agreement with TEM data. [3] A critical advantage to µHXRF is the high energy of incoming and emitted X-rays, which simplifies SiGe volume extraction without a complex model or correlation to other geometrical parameters in the GAA device.

Correlation with electrical results
The ultimate measure of device performance occurs when the wafers are electrically tested, also known as wafer acceptance test (WAT) for foundries. Feedback between metrology, electrical test results, and yield management systems enables critical improvements in CD control.

“When CD data are loaded into an active yield control system, the system can detect trends of worsening CDs between shots or wafers (die-to-die variation usually is associated with a rotational shot misalignment) and warn the litho engineers about this,” said Dieter Rathei, CEO of DR Yield. “But perhaps even more important is the possibility to correlate litho alignment data to functional chip test data. This allows to detect design vulnerabilities against very subtle CD variations.”

Measurement of subtle variations in overlay are possible with specific test structures that use e-beam voltage contrast measurements to monitor and improve alignment and CD variation in BEOL interconnects patterned by double patterning (litho-etch, litho-etch) of metal lines and vias. The method is meant to capture both lithography variability and tiny changes in misalignment due to planarity variations, which is an increasingly common issue in manufacturing.

“We are monitoring the signals from our test structures and looking to quantify CD variation to monitor for potential electrical failures. Using non-contact electrical measurements the test structures can tell us if we are moving closer to the edge of a process window and becoming marginal or not. Customers find it extremely useful, because you get information about every wafer and every die so you can give feedback to the process,” said PDF’s Brozek. “Because the final electrical misalignment is not only a function of a lithography, of patterning. It’s a combination of the etched patterns, film uniformity and CMP, which can have dishing or other non-planarity. Stresses can cause wafer bowing, so when I’m etching a warped wafer, my profile is not going to be perpendicular to the wafer, it is going perpendicular to the chuck, so the pattern can be off even if lithography shows perfect alignment.”

Depending on the product and layer, the test structures have incrementally built-in incremental misalignment of 1, 2, 3 nm, as so on in x and y directions, sometimes we use a fractions of nanometers. The approach characterizes overlay errors between metal lines and metal lines and vias, and helps to establish and monitor the process window for high yield in HVM. Large variations in overlay error, for instance, from Via0 to Metal1 (see figure 2, top row wafers), were reduced by making lithographic process adjustments between metal 1B and V0B (in bottom row wafers) for improved process margin. [2]

Fig. 3: Metal line to via overlay improvements using design-assisted e-beam measurement and control. Source: PDF Solutions

“Using multiplexing schemes, we are getting very high density of structures, thousands of structures, that are addressable. So that allows you to do the experiment, which uses many structures for misalignment in many directions. We mimic double patterning misalignment for advanced technologies that can either go in the scribe line to monitor yield,” Brozek noted.

Advanced packaging
One of the most critical processes in 3D packaging today involves bonding between different wafers, either in a die-wafer or wafer-wafer configuration. The established process today uses thermocompression bonding of micro-bumps, which need to be precisely aligned for proper electrical behavior, yield, and reliability.

“In advanced packaging, the requirements and tolerances on wafer bumps have really gotten a lot stricter. When you go to stacking, customers want these things to mate very, very accurately and repeatedly. So a big requirement is coplanarity,” said John Hoffman, computer vision engineering manager at Nordson Test & Inspection. “They want to understand these contours and the warpage, which historically wasn’t so important. These devices and bumps have to be super planar if you’re going to start stacking them one on top of another, and so you want to really tightly control that.”

Nordson uses an optical technology called phase profilometry to measure the bumps. Hoffman noted that the bump features on the wafer are typically 1/1,000th the size of the wafer itself. “It’s kind of like landing an aircraft on an aircraft carrier that is moving and undulating on the ocean, so they get navigational misalignment from the get-go.”

Substrate or wafer warpage causes similar challenges when it comes to optical metrology, as well, due to the scale difference between the measured feature and the wafer size. “We have critical measurements of interest,” Hoffman said. “The most important are co-planarity and consistent bump height. When you’re stacking die, you need to know that your thousands of bumps are aligned consistently without variability, and they are electrically solid and well connected — but also physically solid for high reliability.”

Fortunately for advanced packaging applications, the optical repeatability and precision in the z direction is better than it is in x and y.

X-ray techniques also are used in production, either on a sampling basis in high-volume manufacturing or in the development and characterization phases when new processes and materials are being adopted. “We’re seeing that HBM is starting to adopt XRD and XRR techniques, partly because we’ve significantly improved throughput of the equipment, but also there’s just a general need for it,” said John Wall, UK site manager at Bruker. “There’s no other way of characterizing the wafers.”

Both CD-SEMs and scatterometry are meeting the challenges of CD measurements, including height measurements in critical structures of GAA FETs and 3D NAND. Extension of OCD to the mid-infrared wavelength gives better contrast between materials, and machine learning is shortening computation times and enabling earlier time-to-results.

CD-SEMs have dialed up the acceleration voltage to better image deep structures, while expanding field-of-view for better precision. But more work is needed to achieve actual profile measurements in production. The good news is the suppliers and chipmakers are not sitting still.


  1. https://semiengineering.com/challenges-grow-for-cd-sems-at-5nm-and-beyond/
  2. Linrong Yang, et al, “Application of e-Beam Voltage Contrast Technique for Overlay Improvement and Process Window Control in Multi-Patterning Interconnect Scheme,” Sept. 2022, J. of Electron ,Devices Society, doi: 10.1109/JEDS.2022.3203125
  3. “Janusz Bogdanowicz, et al, “Model-free Measurement of Lateral Recess in Gate-all-around Transistors with Micro Hard-X-ray Fluorescenece, JM3, J. of Micro/Nanopatterning Materials, and Metrology, July-Sept 2023, Vol 22 (3), doi: 10.1117/1.JMM.22.3.034001

Related Reading
Closing The Test And Metrology Gap In 3D-IC Packages
Finding defects in stacked die is a daunting challenge. Equipment, processes, and methodologies all need modifications, and that’s just for starters.

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