tag: Nordson Test & Inspection

AI Models Transform Defect Inspection And Review, But Can Fail To Scale
By Laura Peters - 09 Jun, 2026 - Comments: 0

Key Takeaways: AI plays a role in improving defect capture rate and distinguishing between yield-killing and nuisance defects. New developments in wafer edge inspection are proving essential to bonded wafer yields. 70% of AI initiatives stall after pilot implementation, but some pitfalls can be avoided. One of the brightest spots in AI use today is the industry’s ability t... » read more

Why Analog And Mixed-Signal Chips Resist Adaptive Test
By Gregory Haley - 09 Jun, 2026 - Comments: 0

Key Takeaways Analog and mixed-signal test remains heavily specification-based because the measurements do not always produce a single expected result. The absence of objective coverage metrics has historically encouraged conservative test flows, which IEEE 2427-2025 begins to address. Separating device behavior from test-path variation is a prerequisite for any adaptive flow—and h... » read more

Smart Test Collides With The Data Chain
By Gregory Haley - 12 May, 2026 - Comments: 0

Key Takeaways: The promise of smart test is a data-chain problem before it is an algorithm problem. A device can pass every checkpoint and still carry a latent defect the test record never captured. As test grows more adaptive, the validity of the measurement environment matters as much as the measurement itself. For years, the test roadmap has pointed toward more adaptive f... » read more

What’s Failing At The Interface
By Gregory Haley - 07 Apr, 2026 - Comments: 0

Key Takeaways The interface is where failures in advanced packaging become visible, but it's increasingly not where they originate. Weak interfaces often don't fail at time zero, but they do degrade due to parametric drift and margin erosion that binary test screens miss entirely. The temporary test interconnect is the largest variable in the measurement chain and must be controlled ... » read more

The One Bit Problem That Can Break a System
By Ann Mutschler - 02 Apr, 2026 - Comments: 2

Key Takeaways: Bit flipping is no longer a rare reliability issue but a systemic risk driven by shrinking process nodes, higher clock speeds, lower voltages, and radiation exposure, leading to silent data corruption and potential system failure. The same mechanisms that cause accidental bit flips can be deliberately exploited through techniques such as clock, voltage, laser, and rowhamm... » read more

Catching Critical Defects In TSVs And Stacked Chips
By Laura Peters - 10 Feb, 2026 - Comments: 0

Key Takeaways Variation is becoming a bigger problem in multi-die assemblies with TSVs and hybrid bonding. Multi-modal approaches are required to test these devices. AI plays a role in improving defect capture rate and distinguishing between yield-killing and false positives. New methods for interconnecting devices using through-silicon vias (TSVs) and hybrid bonding in stac... » read more

Chiplets Add More Inspection And Test Steps
By Anne Meixner - 10 Feb, 2026 - Comments: 0

Key Takeaways Ensuring the reliability of multi-die assemblies requires a variety of approaches to detect subsurface defects. Bonds and interconnects are especially problematic and require more inspection insertions. Ensuring reliability requires connecting fragmented data that is often siloed. The shift to multi-die assemblies is forcing changes in how chips are tested and ... » read more

Metrology Digs Deep To Produce Next-Generation 3D NAND
By Laura Peters - 09 Dec, 2025 - Comments: 1

Each generation of 3D NAND packs about 30% more bits than the previous version, with current devices storing up to 2 terabits of data in a die the size of a fingernail. With new product introductions shrinking from 18 months to every 12 months, chipmakers are constantly innovating to enable this prodigious scaling pace. 3D NAND technology is a core ingredient in mobile phones, solid-state dr... » read more

HBM Leads The Way To Defect-Free Bumps
By Laura Peters - 11 Nov, 2025 - Comments: 0

High-bandwidth memory stands at the forefront of multiple technology developments as a critical enabler of AI, but it is one of the most difficult modules to manufacture. Leading HBM device makers and foundries must simultaneously handle multi-layer chip stacking, die warpage, and shorter product lifecycles that are shrinking from two years down to just one. But perhaps the most formidable c... » read more

Metrology’s Growing Role In Reducing False Defects
By Gregory Haley - 14 Oct, 2025 - Comments: 0

When a good die fails test and gets scrapped, often no one notices, because false failures look identical to real ones. Yet across the industry, these phantom defects are quietly eroding yield, inflating test costs, and masking the true health of manufacturing processes. At advanced nodes and in heterogeneous packaging, where margins are already razor-thin, even minor variations in contact r... » read more

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