Overview of Test Strategies for 3DICs


A new technical paper titled “Design-for-Test Solutions for 3D Integrated Circuits” was published by researchers at Duke University, Arizona State University, and NVIDIA.

“As Moore’s Law approaches its limits, 3D integrated circuits (ICs) have emerged as promising alternatives to conventional scaling methodologies. However, the benefits of 3D integration in terms of lower power consumption, higher performance, and reduced area are accompanied by testing challenges. The unique vertical stacking of components in 3D ICs introduces concerns related to the robustness of bonding surfaces. Moreover, immature manufacturing processes during 3D fabrication can lead to high defect rates in different tiers. Therefore, there is a need for design-for-test solutions to ensure the reliability and performance of 3D-integrated architectures. In this paper, we provide a comprehensive survey of existing testing strategies for 3D ICs. We describe recent advances, including research efforts and industry practice, that address concerns related to bonding defects, elevated power supply noise, fault diagnosis, and fault localization specific to the unique characteristics of 3D ICs.”

Find the technical paper here. Published June 2024.

S. -C. Hung, P. Bhoumik, A. Chaudhuri, S. Banerjee and K. Chakrabarty, “Design-for-Test Solutions for 3D Integrated Circuits*,” in Integrated Circuits and Systems, doi: 10.23919/ICS.2024.3419629.

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