Impact of Clustering Methods On Partitioning Decisions For 3DICs (imec, Université libre de Bruxelles)


A technical paper titled “Impact of gate-level clustering on automated system partitioning of 3D-ICs” was published by researchers at Université libre de Bruxelles and imec. Abstract: "When partitioning gate-level netlists using graphs, it is beneficial to cluster gates to reduce the order of the graph and preserve some characteristics of the circuit that the partitioning might degrade. ... » read more

3DICs: Legalizer Techniques For Better Routing Quality, Fewer DRVs, And Reduced Total Slack With Negligible Runtime Impact


A technical paper titled “On Legalization of Die Bonding Bumps and Pads for 3D ICs” was published by researchers at the Georgia Institute of Technology, NVIDIA Corporation, and the University of Bremen. Abstract "State-of-the-art 3D IC Place-and-Route flows were designed with older technology nodes and aggressive bonding pitch assumptions. As a result, these flows fail to honor the widt... » read more

3D-IC: Operator Learning Framework For Ultra-Fast 3D Chip Thermal Prediction Under Multiple Chip Design Configurations


A new technical paper titled "DeepOHeat: Operator Learning-based Ultra-fast Thermal Simulation in 3D-IC Design" was published (preprint) by researchers at UCSB and Cadence. Abstract "Thermal issue is a major concern in 3D integrated circuit (IC) design. Thermal optimization of 3D IC often requires massive expensive PDE simulations. Neural network-based thermal prediction models can perform ... » read more

Modeling and Thermal Analysis of 3DIC


A new technical paper titled "Heat transfer in a multi-layered semiconductor device with spatially-varying thermal contact resistance between layers" was published by researchers at UT Arlington. "This work presents a theoretical model to determine the steady state temperature distribution in a general M-layer structure with spatial variation in thermal contact resistance between adjacent la... » read more

Artificial intelligence deep learning for 3D IC reliability prediction


New research from National Yang Ming Chiao Tung University, National Center for High-Performance Computing (Taiwan), Tunghai University, MA-Tek Inc, and UCLA. Abstract "Three-dimensional integrated circuit (3D IC) technologies have been receiving much attention recently due to the near-ending of Moore’s law of minimization in 2D IC. However, the reliability of 3D IC, which is greatly infl... » read more

Energy-efficient Non Uniform Last Level Caches for Chip-multiprocessors Based on Compression


Abstract "With technology scaling, the size of cache systems in chip-multiprocessors (CMPs) has been dramatically increased to efficiently store and manipulate a large amount of data in future applications and decrease the gap between cores and off-chip memory accesses. For future CMPs architecting, 3D stacking of LLCs has been recently introduced as a new methodology to combat to performance ... » read more

Chiplet-Based Advanced Packaging Technology from 3D/TSV to FOWLP/FHE


T. Fukushima, "Chiplet-Based Advanced Packaging Technology from 3D/TSV to FOWLP/FHE," 2021 Symposium on VLSI Circuits, 2021, pp. 1-2, doi: 10.23919/VLSICircuits52068.2021.9492335. Abstract: "More recently, "chiplets" are expected for further scaling the performance of LSI systems. However, system integration with the chiplets is not a new methodology. The basic concept dates back well over ... » read more

Characterization Of Micro-Bumps For 3DIC Wafer Acceptance Tests


The strong market needs to embed multiple functionalities from different semiconductor processing technologies into a single system continue to drive demands for more advanced 3DIC packaging technologies. Dimensions of copper pillar micro-bumps are consistently reduced in every new technology node to facilitate the 3D stacking of multiple dies so that overall system performance can be improved.... » read more

Advanced mm-Wave And Terahertz Measurements With Cascade Probe Stations


The strong market needs to embed multiple functionalities from different semiconductor processing technologies into a single system continue to drive demands for more advanced 3DIC packaging technologies. Dimensions of copper pillar micro-bumps are consistently reduced in every new technology node to facilitate the 3D stacking of multiple dies so that overall system performance can be improved.... » read more

Test Setup Optimization And Automation For Accurate Silicon Photonics Wafer Acceptance Production Tests


Implementing energy-efficient optical transceiver modules with silicon photonics (SiPh) and 3DIC technologies will help alleviate the increasing energy consumption for hyperscale data centers. To facilitate effective 3DIC heterogenous integration of these photonics integrated circuits for optical transceivers, high precision, repeatable and reliable SiPh wafer acceptance tests are essential and... » read more

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