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Testability Analysis Based On Ever-Evolving Technology


The complexity of system-on-chip (SoC) designs continues to grow, so the corresponding design-for-test (DFT) logic required for manufacturing has become more advanced. Design teams are challenged by high gate counts and an array of internally developed and third-party IP integrated into their designs. Understanding if one can create high-quality manufacturing tests for these complex designs mus... » read more

Enabling Test Strategies For 2.5D, 3D Stacked ICs


Improved testability, coupled with more tests at more insertion points, are emerging as key strategies for creating reliable, heterogeneous 2.5D and 3D designs with sufficient yield.  Many changes need to fall into place to make side-by-side 2.5D and 3D stacking approaches cost-effective, particularly for companies looking to integrate chiplets from different vendors. Today, nearly all of t... » read more

Testing The Stack: DFT Is Ready For 3D Devices


When existing advanced 2D designs already push the limits of design-for-test (DFT) tools, what hope do developers have of managing DFT for 3D devices? Can anyone afford the tool run time, on-chip area demand, pattern count, and test time? The answer, from an array of experts, is yes, there is a path to a scalable, affordable, and comprehensive DFT solution for 3D ICs. Well-covered strategies... » read more

Automate Memory Test Through A Shared Bus Interface


The use of memory-heavy IP in SoCs for automotive, artificial intelligence (AI), and processor applications is steadily increasing. However, these memory-heavy IP often have only a single access point for testing the memories. A shared bus architecture allows testing and repairing memories within IP cores through a single access point referred to as a shared bus interface. Within this interface... » read more

Software-Driven and System-Level Tests Drive Chip Quality


Traditional semiconductor testing typically involves tests executed by automatic test equipment (ATE). But engineers are beginning to favor an additional late-test pass that tests systems-on-chip (SoCs) in a system context in order to catch design issues prior to end-product assembly. “System-level test (SLT) gives a high-volume environment where you can test the hardware and software toge... » read more

A Practical Approach To DFT For Large SoCs And AI Architectures, Part II


By Rahul Singhal and Giri Podichetty Part I of this article discusses the design-for-test (DFT) challenges of AI designs and strategies to address them at the die level. This part focuses on the test requirements of AI chips that integrate multiple dies and memories on the same package. Why 2.5D/3D chiplet-based designs for AI SoCs? Many semiconductor companies are adopting chiplet-based d... » read more

Preparing For Test Early In The Design Flow


Until very recently, semiconductor design, verification, and test were separate domains. Those domains have since begun to merge, driven by rising demand for reliability, shorter market windows, and increasingly complex chip architectures. In the past, products were designed from a functional perspective, and designers were not concerned about what the physical implementation of the product ... » read more

Smart DFT Infrastructure And Automation Are Key To Managing Design Scaling


This paper describes how using a smarter DFT infrastructure and automation can greatly improve the DFT schedule. A structural DFT infrastructure based on plug-and-play principles is used to enable concurrent DFT development and integration. DFT automation is used to connect and manage the DFT infrastructure to dramatically reduce the risks associated with design scaling and complexity. Highe... » read more

Simplify DFT For Advanced SoCs


The purpose of electronic design automation (EDA) software is to solve SoC design problems and simplify the entire process. For design for test (DFT), this means aiming to streamline the DFT development for today’s large and complex designs. The technologies and methods developed through partnerships between EDA suppliers, foundries, and semiconductor companies should effectively reduce risk,... » read more

More Manufacturing Issues, More Testing


Douglas Lefever, CEO of Advantest America, sat down with Semiconductor Engineering to talk about changes in test, the impact of advanced packaging, and business changes that are happening across the flow. What follows are excerpts of that discussion. SE: What are the big changes ahead in test? Lefever: It's less about inflection points and more like moving from algebra to calculus in the ... » read more

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