Overview of Test Strategies for 3DICs

A new technical paper titled "Design-for-Test Solutions for 3D Integrated Circuits" was published by researchers at Duke University, Arizona State University, and NVIDIA. Abstract: "As Moore's Law approaches its limits, 3D integrated circuits (ICs) have emerged as promising alternatives to conventional scaling methodologies. However, the benefits of 3D integration in terms of lower power co... » read more

Hidden Costs And Tradeoffs In IC Quality

Balancing reliability against cost is becoming more difficult for semiconductor test, as chip complexity increases and devices become more domain-specific. Tests need to be efficient and effective without breaking the bank, while also ensuring chips are of sufficient quality for their specific application. The problem is that every new IC device adds its own set of challenges, from smaller f... » read more

Advanced DFT And Silicon Bring-Up For AI Chips

The AI market is growing quickly, spurring an insatiable demand for powerful AI accelerators. AI chip makers are pressed with aggressive time-to-market goals and need the tools to help them get their chips into the hands of customers as quickly as possible. IC test and silicon bring-up are tasks that can affect both the quality and the time-to-market of AI chips. Different companies are usin... » read more

Connection Perfection

Whether you are a DFT engineer or a SoC designer, connectivity validation will no doubt be a top priority when taking steps to guarantee the functionality and reliability of your device. SoC designs continue to grow in both size and complexity to meet the ever-growing performance and power demands associated with modern technology. To keep up with this fast-paced evolution, the corresponding D... » read more

Designing Automotive ICs For Cybersecurity

The day has already arrived when we need to be concerned about the cybersecurity of our cars. An average modern car includes about 1400 ICs and many of them are used in sophisticated applications, like autonomous driving and vehicle-to-everything (V2X) communication. The security of road vehicles is an important issue to automakers and OEMs but is rooted in the IC devices that power the vehicle... » read more

eFPGA Architectural Improvements That Lower Test Cost And Increase Quality

More than 40 chips have been licensed to use EFLX eFPGA and >20 chips are working in silicon. Big customers like Renesas are planning high volume families of chips using embedded FPGA. As a result, we have gained extensive experience and knowledge in almost 10 years of doing eFPGA especially in production test for cost reduction and reliability improvement. eFPGA DFT and MBIST for high q... » read more

From Known Good Die To Known Good System With UCIe IP

Multi-die systems are made up of several specialized functional dies (or chiplets) that are assembled in the same package to create the complete system. Multi-die systems have recently emerged as a solution to overcome the slowing down of Moore’s law by providing a path to scaling functionality in the packaged chip in a way that is manufacturable with good yield. Additionally, multi-die sy... » read more

Hunting For Hardware-Related Errors In Data Centers

The semiconductor industry is urgently pursuing design, monitoring, and testing strategies to help identify and eliminate hardware defects that can cause catastrophic errors. Corrupt execution errors, also known as silent data errors, cannot be fully isolated at test — even with system-level testing — because they occur only under specific conditions. To sort out the environmental condit... » read more

Testability Analysis Based On Ever-Evolving Technology

The complexity of system-on-chip (SoC) designs continues to grow, so the corresponding design-for-test (DFT) logic required for manufacturing has become more advanced. Design teams are challenged by high gate counts and an array of internally developed and third-party IP integrated into their designs. Understanding if one can create high-quality manufacturing tests for these complex designs mus... » read more

Enabling Test Strategies For 2.5D, 3D Stacked ICs

Improved testability, coupled with more tests at more insertion points, are emerging as key strategies for creating reliable, heterogeneous 2.5D and 3D designs with sufficient yield.  Many changes need to fall into place to make side-by-side 2.5D and 3D stacking approaches cost-effective, particularly for companies looking to integrate chiplets from different vendors. Today, nearly all of t... » read more

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