tag: design for test

Challenges And Outlook Of ATE Testing For 2nm SoCs
By Sriharsha Vinjamury - 08 Aug, 2024 - Comments: 0

The transition to the 2nm technology node introduces unprecedented challenges in Automated Test Equipment (ATE) bring-up and manufacturability. As semiconductor devices scale down, the complexity of testing and ensuring manufacturability increases exponentially. 3nm silicon is a mastered art now, with yields hitting pretty high for even complex packaged silicon, while the transition from 3nm to... » read more

Ensuring Multi-Die Package Quality And Reliability
By Faisal Goriawalla - 08 Aug, 2024 - Comments: 0

Multi-die designs are gaining broader adoption in a wide variety of end applications, including high-performance computing, artificial intelligence (AI), automotive, and mobile. Despite clear advantages, there are new challenges that need to be addressed for successful multi-die realization. This article gives a high-level overview of the multi-die test challenges that go beyond the design p... » read more

Functional Compaction for Functional Test Sequences (Purdue University, I. Pomeranz)
By Technical Paper Link - 17 Jul, 2024 - Comments: 0

A new technical paper titled "Functional Compaction for Functional Test Sequences" was published by IEEE Fellow Irith Pomeranz at Purdue University. Abstract: "The occurrence of silent data corruption because of hardware defects in large scale data centers points to the advantages of applying functional test sequences to detect hardware defects that escape scan-based tests. When using funct... » read more

Overview of Test Strategies for 3DICs
By Technical Paper Link - 26 Jun, 2024 - Comments: 0

A new technical paper titled "Design-for-Test Solutions for 3D Integrated Circuits" was published by researchers at Duke University, Arizona State University, and NVIDIA. Abstract: "As Moore's Law approaches its limits, 3D integrated circuits (ICs) have emerged as promising alternatives to conventional scaling methodologies. However, the benefits of 3D integration in terms of lower power co... » read more

Hidden Costs And Tradeoffs In IC Quality
By Gregory Haley - 08 Feb, 2024 - Comments: 0

Balancing reliability against cost is becoming more difficult for semiconductor test, as chip complexity increases and devices become more domain-specific. Tests need to be efficient and effective without breaking the bank, while also ensuring chips are of sufficient quality for their specific application. The problem is that every new IC device adds its own set of challenges, from smaller f... » read more

Advanced DFT And Silicon Bring-Up For AI Chips
By Lee Harrison - 07 Dec, 2023 - Comments: 0

The AI market is growing quickly, spurring an insatiable demand for powerful AI accelerators. AI chip makers are pressed with aggressive time-to-market goals and need the tools to help them get their chips into the hands of customers as quickly as possible. IC test and silicon bring-up are tasks that can affect both the quality and the time-to-market of AI chips. Different companies are usin... » read more

Connection Perfection
By Ramsay Allen - 07 Nov, 2023 - Comments: 0

Whether you are a DFT engineer or a SoC designer, connectivity validation will no doubt be a top priority when taking steps to guarantee the functionality and reliability of your device. SoC designs continue to grow in both size and complexity to meet the ever-growing performance and power demands associated with modern technology. To keep up with this fast-paced evolution, the corresponding D... » read more

Designing Automotive ICs For Cybersecurity
By Mohammed Abdelwahid - 02 Nov, 2023 - Comments: 0

The day has already arrived when we need to be concerned about the cybersecurity of our cars. An average modern car includes about 1400 ICs and many of them are used in sophisticated applications, like autonomous driving and vehicle-to-everything (V2X) communication. The security of road vehicles is an important issue to automakers and OEMs but is rooted in the IC devices that power the vehicle... » read more

eFPGA Architectural Improvements That Lower Test Cost And Increase Quality
By Geoff Tate - 02 Nov, 2023 - Comments: 0

More than 40 chips have been licensed to use EFLX eFPGA and >20 chips are working in silicon. Big customers like Renesas are planning high volume families of chips using embedded FPGA. As a result, we have gained extensive experience and knowledge in almost 10 years of doing eFPGA especially in production test for cost reduction and reliability improvement. eFPGA DFT and MBIST for high q... » read more

From Known Good Die To Known Good System With UCIe IP
By Manuel Mota - 11 May, 2023 - Comments: 0

Multi-die systems are made up of several specialized functional dies (or chiplets) that are assembled in the same package to create the complete system. Multi-die systems have recently emerged as a solution to overcome the slowing down of Moore’s law by providing a path to scaling functionality in the packaged chip in a way that is manufacturable with good yield. Additionally, multi-die sy... » read more

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