tag: design for test

Revolutionizing Chip Testing: Navigating Bottlenecks
By Vidya Neerkundar - 14 Oct, 2025 - Comments: 0

In today's rapidly evolving semiconductor landscape, System-on-Chips (SoCs) are becoming increasingly complex, integrating multiple processing cores, specialized accelerators and vast memory arrays. This escalating complexity, while enabling incredible functionality, presents significant challenges for Design-for-Test (DFT) engineers. Ensuring the thorough and efficient testing of these intrica... » read more

Making The Most of Test Resources
By Laura Peters - 09 Sep, 2025 - Comments: 0

Semiconductor testing is undergoing multiple paradigm changes at once with the common goals of producing more known good die per month with low test cost. Achieving these goals requires a delicate balance between yield, quality, and test times. There are multiple ways to go about making better use of existing resources, many of which involve an increasing use of design for test (DFT) methods... » read more

Silicon Lifecycle Management Gains Traction, But It’s Complicated
By Ann Mutschler - 28 Aug, 2025 - Comments: 0

Silicon lifecycle management (SLM) is gaining ground in semiconductor design and test by leveraging specialized on-die sensors and analytics engines to improve power, performance, yield, and reliability. Most modern SoCs mitigate the guesswork by leveraging DFT, which includes adding memory built-in self-test (BiST) or improving functional coverage, but these tests were meant for verifying c... » read more

Test Hyperconvergence In Semiconductor Development
By Pawini Mahajan - 12 Aug, 2025 - Comments: 0

Back when semiconductor devices contained only a few thousand gates, manufacturing test was almost an afterthought. The development team threw the chip “over the wall” to the test engineers, who developed a set of test patterns for the manufacturing floor. As this process became more automated and chips became more complicated, test considerations crept into the development flow and design-... » read more

Addressing Silicon Lifecycle Scaling Demands
By Marc Hutner - 10 Jul, 2025 - Comments: 0

In today’s competitive business landscape, navigating complexity can be a decisive advantage, but it also presents significant challenges. Three crucial trends driving the rise of complexity are technology scaling, design scaling and system scaling. Traditionally, Design for Test (DFT) solutions have focused on the die level; however, these challenges present opportunities at the package and ... » read more

Better ATPG To Minimize Chip Test Time And Cost
By Hari Mani - 08 May, 2025 - Comments: 0

As chips get ever bigger and more complex, the electronic design automation (EDA) industry must innovate constantly to keep up. Engineers expect every new generation of silicon to be modeled, simulated, laid out, and checked in about the same time with the same effort, despite the growth in die size and density. One area of particular focus is manufacturing test. Any effort expended to reduce t... » read more

Shift Left In DFT Design
By Jeff Mayer - 08 Apr, 2025 - Comments: 0

The semiconductor industry continues to face numerous challenges as designs approach reticle limits, process nodes evolve and engineering resources become increasingly stretched. It is essential to maintain high productivity and quality throughout the design flow. This keeps projects on schedule, within budget, and ensures they remain high-quality, reliable, yield well and perform as intended. ... » read more

Failure To Launch
By Gregory Haley - 11 Mar, 2025 - Comments: 1

Failure analysis (FA) is an essential step for achieving sufficient yield in semiconductor manufacturing, but it’s struggling to keep pace with smaller dimensions, advanced packaging, and new power delivery architectures. All of these developments make defects harder to find and more expensive to fix, which impacts the reliability of chips and systems. Traditional failure analysis techniqu... » read more

Optimizing DFT With AI And BiST
By Gregory Haley - 12 Feb, 2025 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to explore how AI impacts design for testability, with Jeorge Hurtarte, senior director of product marketing in the Semiconductor Test Group at Teradyne; Sri Ganta, director of test products at Synopsys; Dave Armstrong, principal test strategist at Advantest; and Lee Harrison, director of Tessent automotive IC solutions at Siemens EDA. Wh... » read more

Hyperconvergence Of Design For Test And Physical Design
By Sri Ganta - 11 Feb, 2025 - Comments: 0

By Sri Ganta and Hyoung-Kook Kim In today’s highly competitive semiconductor industry, chip-design companies strive for competitive advantages by optimizing designs for PPA (Power, Performance, Area). Along with the functional logic, design cores also comprise DFT (Design for Test) logic that spreads across the design. The DFT logic also must be optimized for PPA, requiring design implemen... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2026 SMG   |  Terms of Service  |  Privacy Policy