Revolutionizing Chip Testing: Navigating Bottlenecks

In today’s rapidly evolving semiconductor landscape, System-on-Chips (SoCs) are becoming increasingly complex, integrating multiple processing cores, specialized accelerators and vast memory arrays. This escalating complexity, while enabling incredible functionality, presents significant challenges for Design-for-Test (DFT) engineers. Ensuring the thorough and efficient testing of these intricate designs is paramount to product quality and time-to-market.

Traditional DFT methodologies rely heavily on established standards, such as IEEE 1149.1 (JTAG), IEEE 1500 (Core Test), and, more recently, IEEE 1687 (IJTAG), for advanced reconfigurable networks. These standards provide frameworks for accessing and controlling embedded test logic. However, as chips grow, the very mechanisms designed to facilitate testing can become bottlenecks, hindering the speed and efficiency of the entire test process.

The growing bottleneck: Why traditional IJTAG is struggling

Modern SoC designs often feature thousands of individual test instruments, all connected within a sprawling IJTAG network. While powerful, this setup introduces several critical drawbacks that impact test time and cost:

1. Serial Access Overhead: Accessing instruments within the IJTAG network is predominantly a serial operation. This means reading and writing Test Data Registers (TDRs) requires a large number of shift cycles, consuming valuable test time.
2. Time-Consuming Setup and Reconfiguration: Establishing a scan path to reach an instrument deep within the hierarchical network can be a lengthy process. Furthermore, if the network needs to be reconfigured (e.g., to bypass specific segments or enable different paths), this adds even more overhead to the test setup time.
3. Clocking Challenges: As networks grow, closing the half-cycle timing of control signals becomes increasingly tricky. This often necessitates reducing the Test Clock (TCK) speed, further extending the time required for test setup configuration.
4. Retargeting Complexity: Even state-of-the-art retargeting tools, which translate high-level test commands into low-level scan operations, struggle with the sheer size and complexity of very large IJTAG networks. This can lead to significant delays in pattern generation and optimization.

These challenges collectively contribute to longer test times, increased manufacturing costs and potentially delayed product launches. The industry has been in dire need of a solution that can overcome these limitations while seamlessly integrating with existing DFT infrastructures and flows.

Introducing the game changer

Introduced at the International Test Conference 2025, Tessent IJTAG Pro is Siemens’ solution for high-bandwidth IJTAG needs. It elevates the standard set by the original Tessent IJTAG software, offering all its features while introducing groundbreaking enhancements for higher bandwidth applications. This state-of-the-art tool is designed to revolutionize the use of IJTAG patterns and generic data streaming. By transforming traditional serial IJTAG operations into high-speed parallel processes, it significantly boosts efficiency.

It expands the functionality of IJTAG by allowing read and write access to custom hardware, extending its powerful potential into even analog test applications. The seamless integration of these new capabilities within the production-proven Tessent platform makes it a comprehensive and user-friendly solution.

Tessent IJTAG Pro leverages the existing high-speed, parallel Tessent Streaming Scan Network (SSN) bus – a technology already used in many modern chips for efficient test pattern delivery to cores – to accelerate IJTAG operations. The core innovation lies in a new component: the Tessent SSN IJTAG Host (SIH). This specialized component acts as an intelligent interface between the blazing-fast SSN bus and a smaller, localized segment of the IJTAG network, referred to as the “local IJTAG network.” By strategically placing SIHs throughout the design, high-bandwidth IJTAG addresses the challenges mentioned above head-on:

• Parallel Access: Multiple SIHs can be driven in parallel by the SSN bus, allowing independent and simultaneous access to different parts of the IJTAG network. This dramatically reduces the serial access bottleneck.
• Deep Hierarchy Reach: SIHs can be strategically placed anywhere on the SSN bus, even deep within the chip’s hierarchy. This enables them to intercept and manage local IJTAG networks without requiring extensive reconfigurations of the global IJTAG network.
• Faster Local Clocks: Each SIH generates its own version of the TCK for its local IJTAG network. Because these local networks are much smaller, their TCKs can run significantly faster than a global TCK, leading to quicker shift operations.
• Simplified Retargeting: Retargeting tools now only need to consider the much smaller, isolated local IJTAG network managed by an SIH, rather than the entire sprawling global network. This simplifies and accelerates the pattern generation process.

Essentially, Tessent IJTAG Pro combines the high-speed data delivery capabilities of Tessent SSN with the flexibility and configurability of IJTAG, creating a powerful synergy for chip testing.

Fig. 1:  High-bandwidth IJTAG over Tessent SSN.

Generic data streaming

Tessent IJTAG Pro uses the Tessent SSN architecture to cover traditional serial IJTAG operations into high-bandwidth parallel processes, an industry first. Tessent SSN utilizes a symmetric bus architecture for delivering scan ATPG patterns. Parallel processing helps reduce test setup application time while providing high-bandwidth IJTAG and generic data streaming (GDS). The GDS functionality extends the Tessent SSN bus by enabling the transmission of custom data to various generic instruments throughout the design hierarchy.

The Tessent SSN high-speed bus may be reused for generic data delivery, utilizing the same SSH for both scan and generic data streaming, though not concurrently. Pattern delivery is handled via context patterns using IJTAG, and SSH clock generation mirrors that of scan delivery, employing a divided and gated shift capture clock. This approach ensures compatibility with existing scan delivery features, including on-chip compare, streaming through IJTAG, size resolution, DDR clocking and bus scaling. Additionally, data throttling is available but is off by default.

How high-bandwidth IJTAG works: a deep dive

To fully appreciate the power of high-bandwidth IJTAG, let’s explore its architectural details, pattern generation flow and advanced features.

Architectural details: The role of the SIH

The SIH component is the heart of the high-bandwidth IJTAG methodology. It’s a configurable interface that seamlessly integrates with both the SSN bus and the local IJTAG network it hosts. It’s designed to be fully configurable via IJTAG (for initial setup) and partially reconfigurable via SSN (during high-bandwidth IJTAG operation).

Conceptually, high-bandwidth IJTAG introduces two distinct views of the IJTAG network:

1. Global IJTAG network: This is the traditional view, accessible from the top-level I/O or Test Access Port (TAP). It’s primarily used to configure the SIHs and the SSN bus itself.
2. Local IJTAG network: This is a subset of the global network, specifically the portion hosted and controlled by an individual SIH. It’s where high-speed IJTAG operations take place.

The SIH operates in one of three mutually exclusive modes, depending on the chip’s overall state:

1. SSN bypass mode: When Automatic Test Pattern Generation (ATPG) patterns are being delivered through the SSN bus to other components (like Streaming Scan Hosts, SSHs), the SIH acts as a simple SSN pipeline stage, minimizing its impact on the data flow.
2. Global IJTAG mode: In this mode, the top-level I/O/TAP ports are used to access the IJTAG network. The SIH behaves as a standard Segment Insertion Bit (SIB) within the IEEE 1687 framework, allowing access to its hosted local IJTAG network. This mode also serves as a crucial fallback if the SSN bus or SIHs are temporarily unavailable.
3. High-bandwidth IJTAG mode: This is where the magic happens. The SIH takes complete control of its local IJTAG network. It generates a local TCK from the SSN bus clock and local IJTAG control signals from an internal finite state machine. The SIH samples scan-in data from the SSN bus and writes scan-out data back to it. Crucially, SIH configuration registers are accessible and shifted along with the local IJTAG network data, enabling dynamic reconfiguration for optimized test schedules.

Clocking and timing requirements: Localized speed

One of the most significant performance gains in high-bandwidth IJTAG comes from its approach to clocking. While the global IJTAG network may operate at a relatively slow TCK (e.g., 50 MHz), the local IJTAG networks driven by SIHs can run much faster (e.g., 100 MHz or more). This is possible because the SIH generates its local TCK by dividing the high-speed SSN bus clock, and timing closure is performed locally for the smaller network.

The SIH incorporates a special clock generation circuit that can “stretch” the TCK by holding it low and high for extra cycles around critical IJTAG control signal transitions. This allows for a faster TCK during data shifting (when no control signals change) and effectively a slower TCK during timing-critical transitions, optimizing both speed and reliability.

High-bandwidth IJTAG pattern generation: A seamless transition

High-bandwidth IJTAG is designed as a “drop-in replacement” for standard IJTAG. This means that existing IEEE-1687 Procedure Description Language (PDL) operations, which describe read/write operations to instruments, are seamlessly retargeted into high-bandwidth operations that utilize the SSN bus.

The overall pattern generation flow involves several key steps:

1. Structural analysis: The IJTAG network, including the newly inserted SIHs, is analyzed based on its IEEE 1687 Instrument Connectivity Language (ICL) description. This identifies local IJTAG networks and performs critical Design Rule Checks (DRCs).
2. Initial SIH configuration: SIHs are initially configured through the global IJTAG network. This sets parameters such as the SSN bus clock to local TCK ratio and clock stretching cycles. Once configured, SIHs are enabled for high-bandwidth IJTAG mode.
3. Input PDL retargeting: Input PDL operations are then retargeted into high-bandwidth IJTAG operations, which are essentially I/O operations applied through the SSN bus.
4. Fallback to global IJTAG: If certain operations cannot be performed via high-bandwidth IJTAG (e.g., if the target is not within an SIH’s local network), the system automatically reverts to global IJTAG mode. However, minimizing these fallbacks is crucial for maintaining low test time.
5. Final pattern generation: The final test pattern consists of a mix of high-bandwidth IJTAG SSN bus I/O operations, potentially interleaved with global IJTAG operations.

The retargeting process itself is a sophisticated five-step procedure that optimizes the use of the parallel SSN bus:

1. Splitting operations: Input PDL operations are split based on which local IJTAG network they target.
2. Retargeting to SIH boundary: Operations are retargeted to the boundary of the SIH, generating “SIH operations” (scan loads) that the SIH must execute.
3. Scheduling into packets: SIH operations are scheduled into packets, considering “SIH slots” (combinations of bus bit and time phase). Multiple SIHs can share a slot by daisy-chaining their operations.
4. Dynamic SIH configuration: For each packet, the necessary SIH configuration (e.g., bit selection, phase registers) is computed and shifted along with the data, allowing for dynamic reconfiguration.
5. Tessent SSN bus stimuli generation: Finally, the packets are transformed into detailed input stimuli for the SSN bus, including input assignments, output compares and accounting for pipeline delays.

Advanced capabilities: beyond basic access

High-bandwidth IJTAG isn’t just about faster access; it also offers advanced features that further enhance test efficiency:

• Time multiplexing: Since the SSN bus is much faster than local IJTAG TCKs, high-bandwidth IJTAG uses time-division multiplexing. Each SIH reads data only during its assigned “phase” within an SSN bus clock cycle, allowing multiple bits of data to be delivered for a single local TCK cycle.
• Hierarchical SIHs: The architecture supports SIHs within the local IJTAG network of another SIH. A clever “SIH enable synchronization register” ensures proper behavior when turning off high-bandwidth IJTAG mode, preventing invalid patterns due to changing scan paths in hierarchical configurations.
• Broadcast: High-bandwidth IJTAG provides a flexible broadcast mechanism. Multiple SIHs can receive identical operations simultaneously by sharing the same high-bandwidth IJTAG slot. This is highly efficient for operations such as setting up common test modes across multiple cores, thereby avoiding the large fanout and timing issues associated with traditional IJTAG broadcast.

Ensuring robustness: Design Rule Checks

For high-bandwidth IJTAG to function optimally, certain design principles must be followed. New DRCs are implemented to enforce these, primarily ensuring that “local IJTAG networks are fully self-contained.” This means that elements within a local network should not be driven by or drive elements outside that network (i.e., no “side inputs” or “side outputs”).

This self-containment is crucial because local IJTAG networks are modeled and processed independently during retargeting. If connections exist between them, the models would be inaccurate, leading to incorrect patterns. While some exceptions can be made (e.g., for security enable signals), such scenarios can impact performance as they may force temporary fallbacks to global IJTAG mode.

In conclusion

Tessent IJTAG Pro’s high-bandwidth IJTAG technology represents a significant leap forward in chip test and debug efficiency. By ingeniously extending the benefits of the high-speed, parallel Tessent Streaming Scan Network to the serial IJTAG network, high-bandwidth IJTAG combines the best of both worlds.

It offers vastly improved data throughput compared to traditional single-chain serial access, seamlessly integrates into existing IJTAG networks, and provides advanced features such as parallel access, flexible broadcast and localized TCK stretching for faster shift times – all with a remarkably low implementation cost. As chip complexity continues its relentless march, high-bandwidth IJTAG stands as a critical technology for ensuring robust, cost-effective and timely product delivery.

For more information on Tessent IJTAG Pro software, please visit Tessent IJTAG Pro.