tag: scan test

AI-Driven Test Optimization Solves Semiconductor Test Costs And Design Schedules
By Sri Ganta - 08 Feb, 2024 - Comments: 0

Artificial Intelligence has become a pervasive technology that is being applied to solve today’s complex problems, especially in the areas involving exponentially large amounts of data, their analysis, and corresponding decision making that are otherwise limited by human abilities. Therefore, complex challenges in semiconductor design, test and manufacturing are a perfect match for AI. The... » read more

Optimizing Scan Test For Complex ICs
By Gregory Haley - 09 May, 2023 - Comments: 0

As chips become more heterogeneous with more integrated functionality, testing them presents increasing challenges — particularly for high-speed system-on-chip (SoC) designs with limited test pin availability. In addition, the complexity of emerging packages like 3D and chiplets necessitates comprehensive new solutions that can provide faster results at multiple stages in the silicon lifec... » read more

Scan Pattern Portability From PSV To ATE To SLT To IST
By Ash Patel - 30 Jan, 2023 - Comments: 0

By Ash Patel and Karthik Natarajan Chip testing has become increasingly complex due to the number of variables impacting designs – from design size and complexity, to high transistor counts on advanced technology nodes, to 2.5D/3D packaging, to manufacturing variability. All of these combine to make testing today's chips and packages more complicated than ever before. The number of test pa... » read more

Testing The Stack: DFT Is Ready For 3D Devices
By Martin Keim - 08 Sep, 2022 - Comments: 0

When existing advanced 2D designs already push the limits of design-for-test (DFT) tools, what hope do developers have of managing DFT for 3D devices? Can anyone afford the tool run time, on-chip area demand, pattern count, and test time? The answer, from an array of experts, is yes, there is a path to a scalable, affordable, and comprehensive DFT solution for 3D ICs. Well-covered strategies... » read more

Semiconductor Test: Staying Ahead Of Nanodevices
By Tucker Davis - 07 Jun, 2022 - Comments: 0

In the semiconductor fabrication process, engineers continue to innovate, enabling smaller transistors and higher density circuits. The transition to finFETs allowed 7nm and 5nm processes to realize circuits of amazing density, and the progress of nanosheet transistors provides confidence in the future advancement of digital circuit cost reduction and performance improvement. As individual t... » read more

Advanced High Throughput e-Beam Inspection With DirectScan
By PDF Solutions - 08 Mar, 2022 - Comments: 0

Optical inspection cannot resolve critical defects at advanced nodes and cannot detect subsurface defects. Especially at 7nm and below, many yield and reliability killer defects are the result of interactions between lithography, etch, and fill. These defects often will have part per billion (PPB) level fail rates. Conventional eBeam tools lack the throughput to measure PPB level fail rates. A ... » read more

A Practical Approach To DFT For Large SoCs And AI Architectures, Part I
By Rahul Singhal - 11 Jan, 2022 - Comments: 0

The traditional processors designed for general-purpose applications struggle to meet the computing demands and power budgets of artificial intelligence (AI) or machine leaning (ML) applications. Several semiconductor design companies are now developing dedicated AI/ML accelerators that are optimized for specific workloads such that they deliver much higher processing capabilities with much low... » read more

High-Quality Test And Embedded Analytics Are Vital For Secure SoCs
By Lee Harrison - 11 Jan, 2022 - Comments: 0

Applications like as smart cards and devices used in the defense industry require security to ensure that sensitive data is inaccessible to outside agents. This used to be a niche requirement met through custom solutions. However, now that automotive and cyber-physical systems are proliferating, the requirements around secure test and monitoring are becoming mainstream. The current best strateg... » read more

Speeding Up Scan-Based Volume Diagnosis
By Bryon Moyer - 07 Dec, 2021 - Comments: 0

In the critical process known as new-product bring-up, it’s a race to get new products to yield as quickly as possible. But the interplay between increasingly complex aspects of designs and process makes it difficult to find root causes of yield issues so they can be fixed quickly. Advanced processes have very high defectivity, and learning must be fast and effective. While progress has be... » read more

Novel Reversible Chain Diagnosis Improves Resolution
By Jayant D'Souza - 09 Nov, 2021 - Comments: 0

Yield ramp for ICs designed on advanced process technologies faces new challenges because of the very complicated silicon defect types and defect distribution. Yield ramp and yield improvement are not just about profitability and time-to-market, but also have a role in today’s electronics supply chain crisis. That means yield ramp affects not just the IC maker, but the global economy. Ever... » read more

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