Optimizing Scan Test For Complex ICs

New techniques for improving coverage throughout a chip’s lifetime.


As chips become more heterogeneous with more integrated functionality, testing them presents increasing challenges — particularly for high-speed system-on-chip (SoC) designs with limited test pin availability.

In addition, the complexity of emerging packages like 3D and chiplets necessitates comprehensive new solutions that can provide faster results at multiple stages in the silicon lifecycle, from pre-silicon design to post-silicon validation to system-level and in-field testing. This has led to exponential growth in the volume of data required for comprehensive testing, and it has extended test times throughout the manufacturing process and beyond.

All of this has significant implications for manufacturing costs and time-to-market. It has increased pressure on test engineers and test equipment companies to achieve controllability and observability of these complex ICs under test. In addition, there is a push to minimize the associated test data volume.

Test data volume refers to the number of test patterns used during testing. The larger the IC and the more complex its functionality, the greater the number of test patterns required to ensure thorough coverage of the design. As the test data volume grows, it becomes challenging to store and transmit such a massive amount of data efficiently.

To address this challenge, various techniques are being developed. Among them:

  • Advanced compression algorithms reduce the size of test patterns and responses;
  • Optimized scan chain architectures improve test efficiency;
  • Efficient packetizing methods facilitate high-speed data transfer, and
  • Innovative test generation approaches achieve higher fault coverage with fewer patterns.

Another approach is to enhance the parallelism and speed of the testing process. This includes the use of advanced automatic test equipment (ATE) with high-speed digital interfaces, multi-site testing capabilities, and optimized test sequencing algorithms. By maximizing the utilization of available test resources and minimizing the overhead associated with test setup and data transfer, significant reductions in test times can be achieved.

Scan testing is experiencing pretty significant and exciting changes,” says Ed Seng, strategic marketing manager for advanced digital at Teradyne. “The ever-increasing device capability, along with advanced process and package technology, is driving continually higher levels of test data volume. To mitigate the associated test time increase, the DFT industry has been pursuing numerous options for higher speed scan test for the past five years, and we are seeing some consolidation into a few paths. One direction is high-bandwidth “scan network” bus designs, which decouple external I/O from internal scan data delivery, enabling efficiency and speed improvements. The other direction is to enable scan data over existing high-speed I/O (HSIO) interfaces, like PCIe or USB. And what we see now is the combination of these approaches, which interestingly unlocks the ability to run scan tests beyond the typical ATE environment (in system-level test or in-field, for example).”

The adoption of built-in self-test (BiST) and self-diagnosis techniques in IC designs is also on the rise. By incorporating test circuitry within the IC itself, these approaches enable on-chip testing and self-diagnosis, reducing the reliance on external test equipment and streamlining the testing process.

All of these testing strategies must strike a balance between various competing interests in the production process, including access, yield, cost, quality, and time-to-market. Furthermore, chip testing no longer concludes once the chips are shipped from the fabrication facility. Customers increasingly demand silicon lifecycle management (SLM), which continues to gather data throughout the chip’s lifetime. It is necessary to detect aging effects and silicon degradation over time, especially for chips used in safety-critical applications.

“Scan test has been the workhorse of the industry for years. It has served us well, but its value-add has started to peter out — especially for large complex ICs, which are destined for heterogeneous integration,” says Dave Armstrong, principal test strategist at Advantest. “In order to achieve the desired quality goals, a certain test data volume must be sourced and received. The challenge then becomes how to speed this content delivery.”

There are two options for speeding content delivery. One is to use more scan I/O pins, but with today’s complex ICs the number of available pins for testing is decreasing. The other approach quickly gaining widespread adoption is the use of HSIO pins, such as SerDes.

Leveraging the functional HSIO interfaces for scan test when it is not actively communicating with other chips has proven to be a logical and highly effective approach to managing the increase in test data volume of complex ICs and heterogenous packages. Heterogeneous integration allows for the integration of multiple chips or chiplets into a package, enabling a higher density of silicon compared to traditional complex designs. However, this denser integration adds to the challenge of testing for subtle defects in transistors and wires because it includes what only a few years ago was an entire motherboard’s functionality.

“The industry roadmap for test has clearly stated for years that scan compression techniques are running out of steam,” says Armstrong. “With recent rises in pattern depths and test times, the evidence is clear that this approach has “topped off.”

To effectively address these challenges, various aspects of scan test need to be considered, including scan test coverage, test time, signal integrity, power consumption, and DFT design. Efficient data transfer over high-speed interfaces, such as high-speed SerDes interfaces or PCIe, becomes essential for transmitting test data, but the significant increase in test data volume also requires efficient packetization methods to ensure streamlined and reliable data transfer. By employing optimized packetization techniques, the test data can be efficiently organized into smaller packets that can be transmitted more efficiently over the high-speed interfaces.

These packetization methods reduce the overall data volume, and they enhance the reliability and speed of the data transfer process. Efficient packetization minimizes latency, reduces overhead, and optimizes the utilization of available bandwidth, ensuring the test data is transmitted accurately and swiftly between the test equipment and the IC under test. This streamlined data transfer process contributes to improved test efficiency, shorter test times, and enhanced overall productivity in testing complex chips.

“Test used to be an afterthought, or it was an integrated system architecture test that required its own I/O, its own buses, its own special things, and it just added cost to the silicon,” says Rob Knoth, product manager at Cadence. “If you start having tasks using high-speed functional I/O, you unlock a tremendous potential, both for manufacturing test cost reduction, as well as for in-system test availability.”

There are other techniques, as well. “Another new strategy is enabling scan in system-level test systems,” notes Teradyne’s Seng. “This insertion step has historically focused on full mission-mode tests only, but with recent solutions to enable scan test over HSIO interfaces, SLT is providing a new cost-optimization opportunity due to its higher site count test economics. Now customers can keep a high level of coverage but have the flexibility to be able to move it early or later in the process flow.”

Testing through high-speed SerDes circuitry, however, poses specific challenges that must be addressed. Among them are making sure there is sufficient scan test coverage, managing test time and data volume, ensuring signal integrity, and addressing power consumption and thermal issues. Effective test access and comprehensive fault detection require well-designed scan architectures for high-speed interfaces like SerDes. The large amount of test data required for high-speed interfaces can lead to extended test times, impacting production throughput. To maintain signal integrity during SerDes testing, careful consideration of test equipment and conditions is necessary to mitigate external noise and interference. Moreover, managing power consumption and thermal stress during test procedures is crucial to prevent any adverse effects.

Designing SerDes circuits for effective testability involves thoughtful consideration of design-for-test (DFT) techniques to ensure optimal performance and functionality. In support of this, industry standard IEEE 1149.10, also known as the “boundary-scan” standard, provides guidelines for incorporating testability features into SerDes circuits. This includes the integration of boundary scan cells, which provide controllability and observability of internal signals, facilitating efficient testing and fault detection.

IEEE 1149.10 defines circuitry for testing ICs through a high-speed TAP with a packet encoder/decoder and distribution architecture. The standard maintains testability of the functional path and ensures future-proof compatibility with upcoming high-speed protocols. However, the increasing need for high-speed pins in ICs presents a challenge in terms of scan test accessibility. The ideal solution is to repurpose high-speed I/Os or SerDes for scan test, but this requires changes throughout the entire ecosystem, from DFT to ATE, without impacting I/O design or functional operation. Industry players like Teradyne, Advantest, Synopsys, and others are actively working towards an end-to-end solution based on the IEEE 1149.10 standard to address this challenge.

The IEEE 1149.10 standard was introduced to overcome limitations of existing scan test methods, including test data compression (TDC). While successful in reducing test data volume, TDC has its own potential failure modes. Compression-induced faults can occur when the compression algorithm distorts or modifies test patterns, leading to incorrect test results. Additionally, there is a risk of losing test coverage if certain parts of the chip are not adequately addressed by compressed test patterns. Furthermore, errors in the compression/decompression hardware can introduce errors into the test data or fail to properly decompress the patterns.

“It has been impossible for many years to state definitively that we have sufficient coverage for all critical components of the chip using scan techniques,” says Armstrong. “We try to focus the scan using various approaches to help the scan be more ‘aware’ of the environment, but with a goal line now moving to parts per billion, it’s hard to say that these techniques are truly sufficient. From my experience, the only way to truly be comfortable that everything is covered is to test the part using more functional test methods. These can both grow confidence and reduce test times if done correctly.”

Chiplets and 3D
Chiplets add a whole new level of complexity for test. “If you start thinking about a heterogenous system, it’s impossible to assume that every chiplet is going to come from the same test vendor,” says Knoth. “And each EDA vendor has their own proprietary kinds of test compression strategies, so companies really need to have better interoperability between the parts of their systems, sharing of data, translation of data, diagnostic ability, etc. That’s a really important aspect that requires people working together.”

To provide a more comprehensive testing approach, the IEEE 1149.10 standard utilizes a modified boundary scan architecture that allows direct testing of internal nodes and connections within the chip, eliminating the need for specialized hardware or compressed test patterns. This approach detects a wider range of faults and can be more cost-effective and easier to implement than TDC in certain cases.

However, the standard’s applicability is focused primarily on digital networks, and it may not be as effective for testing other circuit types or mixed-signal designs. To address these limitations, standards such as IEEE 1687 for embedded instrumentations and IEEE P1838 for analog and mixed-signal test buses have been developed. These standards offer additional capabilities for testing and verification, particularly in the context of mixed-signal designs.

While the IEEE 1149.10 standard has made significant advancements in IC testing, ongoing developments in standards and techniques are essential to keep pace with the evolving nature and complexity of test and verification.

“Some of that is going to come in the form of standards, because it’s important to all be able to sing off the same hymnal,” adds Knoth. “But the other part of it is that it’s going to have to come more from just openness and flexibility. We’re not going to be able to mandate one high-speed I/O to rule them all. We’ve got to make sure that we’re building flexible enough systems that can adapt to different I/Os and different architectures of chips.”

Chiplets and 3D packaging
The 1149.10 standard is relatively new, but it already is being challenged by the evolution toward heterogenous and 3D packages. Heterogeneous integration, where multiple chiplets are combined in a package, presents new challenges in testing for defects in transistors and wires, especially given the increased scale of functionality within these packages. Both 2.5D and 3D will require new test solutions.

These devices present new design-for-test (DFT) challenges because their test requirements extend from the die-level to the package-level. Traditionally, a system-level test (SLT) was used to test the die and memory assembly, but the integration of these components into a single package shifts the testing of this system from SLT to functional tests on multiple dies.

“It is clear known good die (KGD) is critical for the economics of chiplets to succeed, but a lot remains to be concluded about the optimal manufacturing test strategy,” says Seng. “As chiplet designs slowly begin to proliferate more widely, the new UCIe interface may become the de facto standard, with electrical specs spanning ‘advanced’ vs. ‘standard’ packaging with different performance points. These devices only need to operate with a much shorter reach in a more controlled environment, and the interface standards are designed to include BiST testing, repair (via redundant lines), and training sequences. But it is a delicate balance.”

Key trends for scan test
As device structures and materials increase in complexity, scan test alone no longer offers the total solution for identifying defects. To ensure that all critical components of the chip are thoroughly tested, a comprehensive testing strategy using various techniques — such as scan testing, boundary scan testing, memory BiST, and functional testing — must be employed. These hybrid metrology methods will prevail going forward because no single technique can address all the parameters and measurements needed across the entire process, from design to in-field testing.

Test mobility also will be important. As test data volume packaged over serial interfaces continues to grow exponentially, flexibility in test becomes increasingly important. “One thread of development we see involves very large scan tests,” says Rick Burns, president of Teradyne. “In SLT, I can afford to run a scan test that lasts half an hour, but I couldn’t do that on ATE because it would be cost-prohibitive. But if I have repeated scan failures, it’s very difficult to debut that on a SLT, so I want to be able to move that test back to ATE once I’ve narrowed it down to a particular pattern set where I see some elevated faults. I can use the advanced data analytics tools that most ATEs support to hone in on what’s really going on in my silicon.”

Another trend is the increasing use of machine learning and artificial intelligence (AI) in the scan and test process. Machine learning algorithms can process the incredible amount of test data being generated by complex ICs and heterogenous packaging to help identify and predict potential defects. By using machine learning, test companies can identify patterns and anomalies in the data that may indicate potential faults or performance issues. This can help improve the overall quality of the testing process and reduce the risk of product failures in the field.

There is more collaboration happening in testing, as well, with integration throughout the entire design, manufacturing, and application process, driven by the need to meet stricter failure standards. This shift is breaking down traditional barriers and bringing testing to the forefront of system design discussions. The goal is to make testing more physically aware and tightly integrated into the design flow, as it is a valuable contributor to design schedules and overall performance, power, and area (PPA) optimization. The industry recognizes that the more seamless and intelligent the testing process becomes, the more it will be embraced and relied upon. By leveraging data sharing and integration, the industry can build flexible systems that adapt to different input/output (I/O) interfaces and chip architectures, unlocking new opportunities.

“Test is becoming more a part of system design in terms of EDA tools, in terms of design methodology,” says Knoth. “The more physically aware test can be, the more it’s going to be seen as something that can help design schedules and help PPA and test just becomes part of the design flow.”

While there is still progress to be made, industry experts envision a future where standardized protocols like UCI (Universal Chip Interface) enable the propagation of functional test packages across various interfaces, including PCI Express and chiplets. However, the industry is still in the early stages of this evolution. The rapid pace of change and the multitude of interface improvements and dynamic testing methodologies create an exciting and dynamic environment. These advancements are driven by the changing structure of end products and represent a new wave of innovation that holds immense potential for the future of testing.

“This is all evolving as we speak,” adds Burns. “It’s a really fun time. There’s so much going on. These waves of innovation kind of come and go, and we’re clearly in a new wave of innovation around this whole complexity. The topic, lots of interface improvements, all these tests dynamics that we’re talking about, and they’re all driven by the change in the structure of the end products.”

In the realm of complex IC testing, addressing the challenges of test data volume and test time is paramount. Researchers and engineers are actively exploring innovative solutions such as compression algorithms, advanced test generation techniques, optimized scan chain architectures, and efficient packetization methods.

By reducing test data volume, optimizing test time, and enhancing data transfer over high-speed interfaces, manufacturers can achieve more efficient and cost-effective testing processes. These advancements ultimately contribute to the timely delivery of reliable and high-performance ICs to the market, meeting the demands of ever-evolving technological landscapes.

—Anne Meixner contributed to this article.

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