Optimizing Scan Test For Complex ICs

As chips become more heterogeneous with more integrated functionality, testing them presents increasing challenges — particularly for high-speed system-on-chip (SoC) designs with limited test pin availability. In addition, the complexity of emerging packages like 3D and chiplets necessitates comprehensive new solutions that can provide faster results at multiple stages in the silicon lifec... » read more

The Week In Review: Design

M&A Altair acquired Runtime Design Automation. Founded in 1995, Runtime provides tools for optimizing usage of EDA tools, including flow management, job scheduling, and license utilization, as well as tools for optimizing HPC network resources. Altair's focus is on engineering simulation, with tools for HPC resource management and IoT data analytics. Terms of the deal were not disclosed. ... » read more

The JTAG Connection

It is fairly common knowledge that hacking into today’s intelligent Internet devices is child’s play in most cases. The main reason is that the devices have little or no innate security designed in. When they do have some level of security, it is generally provisioned by software running on the host system, to which the devices are connected. But that only works with a device on the grid. O... » read more