The Week In Review: Design

Altair buys Runtime; boundary scan; interconnects; RISC-V.


Altair acquired Runtime Design Automation. Founded in 1995, Runtime provides tools for optimizing usage of EDA tools, including flow management, job scheduling, and license utilization, as well as tools for optimizing HPC network resources. Altair’s focus is on engineering simulation, with tools for HPC resource management and IoT data analytics. Terms of the deal were not disclosed.

Corelis released the latest version of its ScanExpress Boundary-Scan Tool Suite. Version 8.5 adds support for continuous logging of sampled data to file in Debugger, user interface enhancements for the Viewer fault identification system, improved MSP430 & NANDrive device support, and two new processor support packages for ScanExpress JET.

ArterisIP unveiled the latest version of its Ncore Cache Coherent Interconnect. Ncore 3 is a distributed heterogeneous cache coherent on-chip interconnect that allows both AMBA CHI and ACE processor clusters and accelerators to operate as fully coherent peers in the same chip. A CCIX controller allows scaling of coherent systems across multiple chips via the Synopsys DesignWare Controller and PHY IP for PCIe and CCIX. A Resilience Package for functional safety is also available.

NetSpeed announced its technology for optimizing SoC interconnects using supervised machine learning to explore patterns in interconnect design data. The Turing technology has architects specify IP blocks, basic connectivity, performance requirements, and system-centric use cases, then uses machine learning to find optimum solutions. Each use case is evaluated for PPA, FuSa requirements, and an interconnect implementation is suggested.

SiFive launched U54-MC Coreplex IP, a RISC-V based, 64-bit, quadcore real-time capable application processor with support for full featured operating systems such as Linux. The cores utilize a five-stage in-order pipeline, support the RV64GC ISA and cache coherence. It is targeted at AI, machine learning, networking, gateways and smart IoT devices.

Synopsys debuted verification IP and a UVM source code test suite to support the latest USB 3.2 specification. The VIP includes built-in comprehensive coverage, verification plan, protocol checks and integration with protocol-aware debug.

Cadence won a deal with Fuji Xerox, which used Cadence’s Genus Synthesis tool in the development of its multi-functional printer SoCs. Fuji Xerox cited a reduction in timing closure schedule and area, with an 8% total chip area reduction.

Efabless and Silego are running a mixed-signal design challenge. Participants are asked to create a series of ten designs implementing well-used functions in Silego’s GreenPAK CMICs and its software GUI with the efabless platform serving as the crowd source design platform. The contest runs through Dec. 11.

DVCon Europe: Oct. 16-17 in Munich, Germany. The annual conference for design and verification features keynotes by Bosch’s Horst Symanzik on the design challenges of consumer MEMS products, plus a discussion of virtual prototyping of automotive electronics by Audi’s Berthold Hellenthal.

Arm TechCon: Oct. 24-26 in Santa Clara, CA. The Arm ecosystem-focused conference features a number of keynotes from Arm on subjects from the value of IoT data to state-of-the-art silicon process technologies. Invited speakers Stacey Higginbotham, Mary Aiken, and Jessica Barker will discuss the key challenges facing IoT and why a more human-centered approach is needed when designing security.