Week In Review: Design, Low Power


Achronix and Mentor uncorked an optimized HLS flow for Achronix's FPGA technology products. The integrated development environment enables designers to quickly go from C++ to FPGA using Mentor's Catapult HLS and Achronix's ACE design tools. Initially used for 5G wireless applications to reduce the overall development effort and improve QoR, it is suitable for any design targeting Achronix techn... » read more

Week in Review: IoT, Security, Auto


Deals SoftBank Corp. reached an agreement with Indonesia’s Link Net to work together on Internet of Things technology. Hidebumi Kitahara of SoftBank said in a statement, “The global mobile industry is now entering the 5G era, with IoT becoming the central focal point of innovation. This partnership with Link Net shows our strong commitment to further boost technology innovation in the glob... » read more

Week In Review: Design, Low Power


M&A Siemens acquired Austemper Design Systems, which provides tools for functional safety and safety-critical designs. Founded in 2015, Texas-based Austemper adds state-of-the-art safety analysis, auto-correction and fault simulation technology to address random hardware faults, as well as correct and harden vulnerable areas, subsequently performing fault simulation to ensure the design is... » read more

The Week In Review: Design


M&A IoT-focused memory chipmaker Adesto Technologies acquired S3 Semiconductors, a provider of mixed-signal and RF ASICs and IP. Based in Ireland, S3 Semiconductors was founded in 1986. S3 Semiconductors will become a business unit of Adesto and will continue to operate under its current model in the $35 million deal. S3 Semiconductor's parent company, S3 Group, will continue as a separate... » read more

The Week In Review: Design


Tools Mentor, a Siemens business, filled in the last of the hardware configurations for its Veloce Strato emulation family, creating a full upgrade path. Users can initially purchase only the hardware that they need (StratoTiL) and if later they require more capacity (StratoTi) or the ability to handle larger designs (StratoT), they can incrementally add the necessary hardware to their existin... » read more

Heterogeneous Hubbub


It’s no secret that designers today would prefer not to be restricted in their architectural choices. And who can blame them? At the same time, this sentiment has boosted interest and usage of both heterogenous architectures as well as the RISC-V ISA. To support this, companies across the design, test and verification ecosystem are ramping efforts. One such effort is the teaming of UltraSo... » read more

RISC-V Gains Its Footing


The RISC-V instruction-set architecture, which started as a UC Berkeley project to improve energy efficiency, is gaining steam across the industry. The RISC-V Foundation's member roster gives an indication who is behind this effort. Members include Google, Nvidia, Qualcomm, Rambus, Samsung, NXP, Micron, IBM, GlobalFoundries, UltraSoC, Siemens, among many others. One of the key markets for... » read more

Blockchain: Hype, Reality, Opportunities


Blockchain buzz has reached deafening levels, and its proponents say we haven’t heard anything yet. The blockchain-enabled transformations they describe make the Internet revolution look almost trivial. Critics argue that too many people drank the blockchain Kool-Aid. Outside the cryptocurrency arena, they say that blockchain amounts to little more than some really slick slideware. The ... » read more

Reflection On 2017: Design And EDA


People love to make predictions, and most of the time they have it easy, but at Semiconductor Engineering, we ask them to look back on the predictions they make each year and to assess how close to the mark they were. We see what they missed and what surprised them. Not everyone accepts our offer to grade themselves, but most have this year. (Part one looked at the predictions associated with s... » read more

Mixing Interface Protocols


Continuous and pervasive connectivity requires devices to support multiple interface protocols, but that is creating problems at multiple levels because each protocol is based on a different set of assumptions. This is becoming significantly harder as systems become more heterogeneous and as more functions are crammed into those devices. There are more protocols that need to be supported to ... » read more

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