Week In Review: Design, Low Power

Arm Neoverse Compute Subsystems (CSS); Cadence kits for Neoverse design; chessboard improve qubit addressing; $53B AI chip revenue.


Design & IP

Arm launched the Neoverse Compute Subsystems (CSS), pre-integrated and validated configurations of Arm Neoverse platform IP, at this week’s Hot Chips conference. CSS helps streamline SoC designs for data centers and is optimized for an advanced 5nm process. The first generation of CSS (Neoverse CSS N2) is based on Arm’s Neoverse N2 platform. Core count is configurable (24 to 32, up to 64 Neoverse N2-cores) at core frequencies of 2.1GHz up to 3.6Ghz. The core supports Armv9 instructions for vector processing and ML, enhanced cryptography, memory partitioning and monitoring, and advanced power management.

Cadence is offering 5nm and 3nm rapid adoption kits (RAKs) for data center chips based on Arm Neoverse V2 platform. The RAKs cover RTL-to-GDS digital full flow and use AI to speed up some of the tasks.

New concepts are needed for security verification in IC designs, but it is difficult to ensure that hardware works correctly and is capable of detecting vulnerabilities that may show up in the field. Here’s why.

SiFive introduced its RISC-V P870 core at Hot Chips this week.

The Fraunhofer Institute for Photonic Microsystems IPMS announced its RISC-V processor core IP, called EMSA5-FS. It features a 32-bit processor with a five-stage pipeline. The IP can be used in embedded systems, including functional safety applications in the automotive sector. The automotive version of the IP core has an ASIL D-ready certification, according to ISO 26262.

Component-level workflows are still being developed for automotive. And while it’s possible to shift more left in the design flow with faster tools and more compute resources in the data center, the next generation of issues that need to be solved are a bit different.

Read the latest design and verification tech papers:

  • An Open-Source Solution To Accelerate Autonomous Vehicle Validation And Verification Research
  • An Open-Source Hardware Design And Specification Language To Improve Productivity And Verification
  • Formally Modeling A Security Monitor For Virtual Machine-Based Confidential Computing Systems (IBM)
  • EDA Tool To Detect SW-HW Vulnerabilities Ensuring Data Confidentiality In A RISC-V Architecture

Products & deals

Intel uncorked new versions of its Xeon product family at Hot Chips, including a new architecture for its next-generation server platforms due out in 2024. Code-named Sierra Forest, it will have the Efficient-cores (E-cores) with density-optimized compute. The P-cores (Performance-cores, which have been in use in Xeons for a while) will be in the new Xeon versions, code-named Granite Rapids. The 5th Gen Xeon (code-named Emerald Rapids) is slated to launch in Q4. Intel says Sierra Forest, which support 1S and 2S servers in data centers, will have 2.5X greater rack density and 2.4X higher performance per watt.

How do you understand if your manufacturing data from the fab or any data that has gone through AI algorithms is good and your results are accurate? Can the results be proven and repeated? Experts explain how far along the semi industry is with checking AI and how it fits into manufacturing.

Keysight helped run and participated in the first summit for Open Testing and Integration Centers (OTICs) — of which there are 15 globally. The summit is for members of the global Open RAN ecosystem and features some of Keysights solutions for testing energy use and security of O-RAN systems. Keysight co-organized the first Global Open Testing and Integration Centers (OTIC) Summit with the Singapore University of Technology and Design (SUTD), and the Infocomm Media Development Authority (IMDA), in close partnership with O-RAN Alliance.

Nine large Chinese companies engaged in chip design formed a “patent protection alliance” to protect their RISC-V designs. They also agreed not to sue each other over patent infringement. The deal emanated from a RISC-V forum in China, according to a story in the South China Morning Post (SCMP).

Power and performance

Read the latest power and performance tech papers:

  • An Energy-Efficient 10T SRAM In-Memory Computing Macro Architecture For AI Edge Processor
  • An Open-Source Hardware Design And Specification Language To Improve Productivity And Verification
  • Distributed Batteries Within A Heterogeneous 3D IC To Optimize Performance
  • Remote Direct Memory Introspection (Rice, Duke, MIT)

Read the latest optoelectronics / photonics tech papers:

  • Modeling Optical Loss And Crosstalk Noise For Silicon-Photonic-Based Neural Networks Of Different Scales
  • How Band Nesting Can Achieve Near-Perfect Optical Absorption In Just Two Layers Of TMD Materials
  • Performance Enhancement Of An Si Photodetector By Incorporating Photon-Trapping Surface Structures

Market research

Gartner forecasts AI chip revenue will reach $53B worldwide in 2023, a 20.9% from 2022, says the research firm.

Research notes

Researchers from Delft University of Technology were inspired by a chessboard in their method of controlling the addressing of quantum dots. Quantum dots hold the qubits, each of which currently needs its own control electronics and addressing lines. The chessboard approach makes it possible to address quibits by vertical and horizontal lines. The researchers are part of QuTech—a collaboration between the TU Delft and TNO.

A team from the University of Innsbruck and the Institute of Quantum Optics and Quantum Information (IQOQI)of the Austrian Academy of Sciences have shown that quantum entanglement can improve accuracy of the measurements in sensors. The team used lasers on ions lined up in a vacuum chamber. The lasers tuned the interaction among the ions and entangled them into a squeezed quantum state. The method could be useful in applications that currently use atomic clocks, such as satellite-based navigation or data transfer.

Upcoming Events

For more events, go to the event calendar.

  • IEEE International System-on-Chip Conference (SOCC): SoCs/ SiPs for Edge Intelligence & Accelerated Computing, September 5 – 8 (Santa Clara, CA)
  • SEMICON Taiwan, September 6 – 8 (Taipei)
  • DVCON Taiwan, September 7 (Hsinchu, Taiwan)
  • AI Hardware Summit 2023, September 12 – 14 (Santa Clara, CA)
  • CadenceLIVE Boston 2023, September 12 (Boston, MA)

Further reading

Check out the latest Low Power-High Performance and Systems & Design newsletters for these highlights and more:

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