Chip Industry Week In Review

By The SE Staff - 26 Jul, 2024 - Comments: 0

The U.S. Department of Commerce and Amkor Technology signed a deal to provide up to $400 million in funding, under the CHIPS and Science Act, to build a previously announced end-to-end advanced packaging plant. The combined funding is expected to total about $2 billion. The new facility will add some 2,000 jobs in Peoria, Arizona. The SK hynix Board approved its Yongin Semiconductor Cluster... » read more

The Value Of Innovation

By Brian Bailey - 27 Jun, 2024 - Comments: 1

This week's Design Automation Conference is all about the new things that are going on in the industry, both challenges and opportunities. By this time this blog goes live, I will have moderated a panel about why EDA has not been open to disruption. While preparing for that, a number of thoughts emerged in my mind. First, we have to remember that EDA is a business whose role is to support th... » read more

RISC-V Verification: From Simulation To Formal

By Ashish Darbari - 27 Jun, 2024 - Comments: 0

Axiomise's Nicky Khodadad and Ashish Darbari discuss simulation and the need for formal verification and RISC-V, including why simulation-based verification is inadequate to find all the bugs in a design and how formal verification can help with bug hunting for corner-case bugs and exhaustive proofs of bug absence. » read more

An LLM Approach For Large-Scale SoC Security Verification And Policy Generation (U. of Florida)

By Technical Paper Link - 26 Jun, 2024 - Comments: 0

A technical paper titled “SoCureLLM: An LLM-driven Approach for Large-Scale System-on-Chip Security Verification and Policy Generation” was published by researchers at the University of Florida. Abstract: "Contemporary methods for hardware security verification struggle with adaptability, scalability, and availability due to the increasing complexity of the modern system-on-chips (SoCs). ... » read more

Chip Industry Week In Review

By The SE Staff - 21 Jun, 2024 - Comments: 0

BAE Systems and GlobalFoundries are teaming up to strengthen the supply of chips for national security programs, aligning technology roadmaps and collaborating on innovation and manufacturing. Focus areas include advanced packaging, GaN-on-silicon chips, silicon photonics, and advanced technology process development. Onsemi plans to build a $2 billion silicon carbide production plant in the ... » read more

Rowhammer Bit Flips On A High-End RISC-V CPU (ETH Zurich)

By Technical Paper Link - 13 Jun, 2024 - Comments: 0

A new technical paper titled "RISC-H: Rowhammer Attacks on RISC-V" was published by researchers at ETH Zurich. RISC-H will be presented at DRAMSec (co-located with ISCA 2024) Abstract: "The first high-end RISC-V CPU with DDR4 support has been released just a few months ago. There are currently no Rowhammer studies on RISC-V devices and it is unclear whether it is possible to compromise ... » read more

When To Expect Domain-Specific AI Chips

By Brian Bailey - 13 Jun, 2024 - Comments: 0

The chip industry is moving toward domain-specific computation, while artificial intelligence (AI) is moving in the opposite direction, creating a gap that could force significant changes in how chips and systems are architected in the future. Behind this split is the amount of time it takes to design hardware and software. In the 18 months since ChatGPT was launched on the world, there has ... » read more

Efficient TNN Inference on RISC-V Processing Cores With Minimal HW Overhead

By Technical Paper Link - 10 Jun, 2024 - Comments: 0

A new technical paper titled "xTern: Energy-Efficient Ternary Neural Network Inference on RISC-V-Based Edge Systems" was published by researchers at ETH Zurich and Universita di Bologna. Abstract "Ternary neural networks (TNNs) offer a superior accuracy-energy trade-off compared to binary neural networks. However, until now, they have required specialized accelerators to realize their effic... » read more

Using Formal Verification To Evaluate The HW Reliability Of A RISC-V Ibex Core In The Presence Of Soft Errors

By Technical Paper Link - 31 May, 2024 - Comments: 0

A technical paper titled “Using Formal Verification to Evaluate Single Event Upsets in a RISC-V Core” was published by researchers at University of Southampton. Abstract: "Reliability has been a major concern in embedded systems. Higher transistor density and lower voltage supply increase the vulnerability of embedded systems to soft errors. A Single Event Upset (SEU), which is also calle... » read more

RISC-V Heralds New Era Of Cooperation

By Brian Bailey - 30 May, 2024 - Comments: 0

RISC-V is paving the way for open source to become accepted within the hardware community, creating a level of industry collaboration never seen in the past, while revitalizing the connection between academia and industry. The big question is whether this arrangement is just a placeholder while the industry re-learns how to develop processors, or whether this processor architecture is someth... » read more

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tag: RISC-V

Chip Industry Week In Review

The Value Of Innovation

RISC-V Verification: From Simulation To Formal

An LLM Approach For Large-Scale SoC Security Verification And Policy Generation (U. of Florida)

Chip Industry Week In Review

Rowhammer Bit Flips On A High-End RISC-V CPU (ETH Zurich)

When To Expect Domain-Specific AI Chips

Efficient TNN Inference on RISC-V Processing Cores With Minimal HW Overhead

Using Formal Verification To Evaluate The HW Reliability Of A RISC-V Ibex Core In The Presence Of Soft Errors

RISC-V Heralds New Era Of Cooperation

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