Blog Review: May 31


Mentor's Michael White predicts that 10nm will come on the scene in a big way this year with a leap to an estimated 9% foundry market share. At the recent RISC-V Workshop, Cadence's Paul McLellan considers whether fully open-source silicon is really viable. Synopsys' Robert Vamosi investigates the security risks posed by the proliferation of connected aftermarket automotive products and a... » read more

RISC-V Pros And Cons


Simpler, faster, lower-power hardware with a free, open, simple instruction set architecture? While it sounds too good to be true, efforts are underway to do just that with RISC-V, the instruction-set architecture (ISA) developed by UC Berkeley engineers and now administered by a foundation. It has been known for some time that with [getkc id="74" comment="Moore's Law"] not offering the same... » read more

The Week In Review: Design


Tools Synopsys debuted a tool to replay RTL simulation data on a gate-level netlist for power analysis the company says is accurate within 5% of signoff. The tool, PowerReplay, is design to be used in combination with PrimeTime PX gate-level power analysis for earlier and faster generation of gate-level switching data. IP ClioSoft launched a design reuse ecosystem for searching and com... » read more

The Week In Review: Design


IP ARM launched the Mali-C71 image signal processor (ISP), targeting ADAS SoCs. The ISP is capable of processing up to 4 real-time cameras and 16 camera streams with a single pipeline and provides advanced error detection with more than 300 dedicated fault detection circuits. Included is full reference software to control the ISP, sensor, auto white balance and auto exposure. Synopsys ext... » read more

Memory Model Verification at the Trisection of Software, Hardware, and ISA (Princeton)


Source: Princeton University, Caroline Trippel, Yatin A. Manerkar, Daniel Lustig*, Michael Pellauer*, Margaret Martonosi *NVIDIA Princeton University researchers have discovered a series of errors in the RISC-V instruction specification that now are leading to changes in the new system, which seeks to facilitate open-source design for computer chips. In testing a technique they created for... » read more

System Bits: April 18


RISC-V errors Princeton University researchers have discovered a series of errors in the RISC-V instruction specification that now are leading to changes in the new system, which seeks to facilitate open-source design for computer chips. In testing a technique they created for analyzing computer memory use, the team found over 100 errors involving incorrect orderings in the storage and retr... » read more

54th DAC Program Finalized


A DAC winter meeting held in sunny Mexico isn’t what it’s cracked up to be. (Although we did enjoy the break from this winter storms!) Everybody thinks the Executive Committee members are lounging on the beach enjoying drinks with little umbrellas in them. That couldn’t be further from the truth! In fact, I and 15 other EC members spent most of our February meetings in Puerto Vallar... » read more

The Week In Review: Design


IP Arastu Systems uncorked a LPDDR3 DRAM Memory Controller. The controller is fully compliant with JEDEC standard JESD209-3C and supports various power down modes as well as multiple channels with a privilege to configure and manage each channel independently and parameterized data width. CSEM's Bluetooth Low Energy silicon RF IP has been validated as Bluetooth 5 compatible. RF test equip... » read more

SiFive: Low-Cost Custom Silicon


One of the lessons learned years ago in the open-source Linux world is that free software isn't always good enough. Consequently, being able to add commercial value around freeware can turn into a lucrative business. Red Hat Software, for example, has turned this approach into a thriving multi-billion-dollar business. But nothing comparable has ever succeeded in the SoC world. Enter SiFi... » read more

The Week In Review: Design


Deals Kilopass extended its deal with ICScape, which makes a Parallel SPICE simulator, for eNVM IP at advanced finFET nodes. Kilopass has been working with ICScape for the past couple of years as part of its qualification methodology. IP Silvaco released three MIPI I3C sensor controller IP cores. Developed with NXP to push adoption of I3C, the new products are an Advanced Slave core wi... » read more

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