tag: RISC-V

System State Challenges Widen
By Brian Bailey - 30 Nov, 2023 - Comments: 0

Knowing the state of a system is essential for many analysis and debug tasks, but it's becoming more difficult in heterogeneous systems that are crammed with an increasing array of features. There is a limit as to how many things engineers can keep track of, and the complexity of today's systems extends far beyond that. Hierarchy and abstraction are used to help focus on the important aspect... » read more

The Evolution Of RISC-V Processor Verification: Open Standards And Verification IP
By Imperas - 29 Nov, 2023 - Comments: 0

The OpenHW Group’s [1] Verification task group has been a pioneer in the development of methodologies and verification collateral for RISC-V processor verification. Since 2019 the members have worked together to develop CORE-V-VERIF: a UVM environment for the verification of RISC-V processor cores. Over this period of time the CORE-V-VERIF environment has evolved as new processor verification... » read more

Fast Interrupt Extension For MCU RISC-V
By Technical Paper Link - 20 Nov, 2023 - Comments: 0

A technical paper titled “CV32RT: Enabling Fast Interrupt and Context Switching for RISC-V Microcontrollers” was published by researchers at ETH Zurich and University of Bologna. Abstract: "Processors using the open RISC-V ISA are finding increasing adoption in the embedded world. Many embedded use cases have real-time constraints and require flexible, predictable, and fast reactive handl... » read more

Coding And Debugging RISC-V
By Ann Mutschler - 06 Nov, 2023 - Comments: 0

As monolithic device scaling continues to wind down and evolve toward increasingly heterogeneous designs, it has created an inflection point for chip architects to create customized cores that are much more energy efficient and faster than off-the-shelf processors. Zdeněk Přikryl, CTO of Codasip, talks about where RISC-V fits into this picture, using a modular ISA and custom instruction layer... » read more

Potentials And Issues Of Designing Fault-Tolerant Hardware Acceleration For Edge-Computing Devices
By Technical Paper Link - 31 Oct, 2023 - Comments: 0

A technical paper titled “Fault-Tolerant Hardware Acceleration for High-Performance Edge-Computing Nodes” was published by researchers at University of Rome. Abstract: "High-performance embedded systems with powerful processors, specialized hardware accelerators, and advanced software techniques are all key technologies driving the growth of the IoT. By combining hardware and software tec... » read more

CPU Fuzzing Via Intricate Program Generation (ETH Zurich)
By Technical Paper Link - 31 Oct, 2023 - Comments: 0

A technical paper titled “Cascade: CPU Fuzzing via Intricate Program Generation” was published by researchers at ETH Zurich. Abstract: "Generating interesting test cases for CPU fuzzing is akin to generating programs that exercise unusual states inside the CPU. The performance of CPU fuzzing is heavily influenced by the quality of these programs and by the overhead of bug detection. Our a... » read more

FIR And Median Filter Accelerators In CodAL
By Codasip - 25 Oct, 2023 - Comments: 0

5G is the latest generation of cellular networks using the 3rd Generation Partnership Project (3GPP) 5G New Radio air interface. Unlike previous generations of network (2G, 3G & 4G) which had a one-size-fits-all approach, 5G aims to address a wide range of very different applications. To flexibly support diverse quality of service requirements, network slicing is introduced to enable mul... » read more

FPGA-Proven RISC-V System With Hardware Accelerated Task Scheduling
By Technical Paper Link - 24 Oct, 2023 - Comments: 0

A technical paper titled “Enabling HW-based Task Scheduling in Large Multicore Architectures” was published by researchers at Barcelona Supercomputing Center, University of Campinas, University of Sao Paulo, and Arteris Inc. Abstract: "Dynamic Task Scheduling is an enticing programming model aiming to ease the development of parallel programs with intrinsically irregular or data-dependent... » read more

Verifying A RISC-V Processor
By Ed Sperling - 17 Oct, 2023 - Comments: 0

Verifying an SoC is very different than verifying a processor due to the huge state space in the processor. In addition to the tools needed for an SoC, additional tools are required for a step and compare environment. Larry Lapides, vice president at Imperas, talks about the need to verify asynchronous events like interrupts, how to compare a reference model to RTL, and the need for both hardwa... » read more

Chip Industry Week In Review
By The SE Staff - 13 Oct, 2023 - Comments: 0

By Liz Allan, Jesse Allen, and Karen Heyman. Canon uncorked a nanoimprint lithography system, which the company said will be useful down to about the 5nm node. Unlike traditional lithography equipment, which projects a pattern onto a resist, nanoimprint directly transfers images onto substrates using a master stamp patterned by an e-beam system. The technology has a number of limitations and... » read more

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