Trimming Waste In Chips


Extra circuitry costs money, reduces performance and increases power consumption. But how much can really be trimmed? When people are asked that question they either get defensive or they see it as an opportunity to show the advantages of their architecture, design process or IP. The same holds true for IP suppliers. Others point out that the whole concept of waste is somewhat strange, becau... » read more

The Week In Review: Design


M&A Altair acquired Runtime Design Automation. Founded in 1995, Runtime provides tools for optimizing usage of EDA tools, including flow management, job scheduling, and license utilization, as well as tools for optimizing HPC network resources. Altair's focus is on engineering simulation, with tools for HPC resource management and IoT data analytics. Terms of the deal were not disclosed. ... » read more

The Week In Review: Design


Tools Cadence unveiled an integrated memory design and verification tool, with environments for bitcell design, array and complier verification, and memory characterization. It utilizes existing simulation databases for multi-corner and Monte Carlo analysis, which the company says can lead to a 2X runtime improvement. Solido Design Automation uncorked PVTMC Verifier, which uses machine lear... » read more

The Week In Review: IoT


Deals Advanced Semiconductor Engineering was selected by zGlue as its strategic manufacturing partner. The ASE Group will make the zGlue Integrated Platform, which is said to enable customization for consumer and industrial IoT markets. The ZiP integrates hardware and software in a modular 3DIC-based platform. ASE will assemble zGlue-certified chiplets for connecting through zGlue Smart Fabric... » read more

The Week In Review: Design


Tools Ansys updated its simulation suite, improving the speed of PCB and electronic package simulation as well as integrating its embedded systems tool with its failure analysis capabilities. Other updates include a new visual ray tracing capability to aid in antenna placement, improved modeling of the quality of wireless links in the presence of electromagnetic interference and RF interferenc... » read more

IP Challenges Ahead


The revenue from semiconductor [getkc id="43" kc_name="IP"] has risen steadily to become the largest segment of the EDA industry. Industry forecasts expect it to keep growing at a CAGR of more than 10% for the next decade. Part one of this article examined the possibility those forecasts are wrong and that large semiconductor companies are likely to start bringing IP development back in hous... » read more

Is The IP Industry Healthy?


The semiconductor industry has been through many changes, each designed to reduce the total cost associated with the design and manufacture of chips. Twenty years ago, most companies had their own fabs and designed all of the circuitry on each chip. Today, only a handful of companies still own a fab and outsourcing design, in the form of intellectual property ([getkc id="43" kc_name="IP"]), has... » read more

Blog Review: May 31


Mentor's Michael White predicts that 10nm will come on the scene in a big way this year with a leap to an estimated 9% foundry market share. At the recent RISC-V Workshop, Cadence's Paul McLellan considers whether fully open-source silicon is really viable. Synopsys' Robert Vamosi investigates the security risks posed by the proliferation of connected aftermarket automotive products and a... » read more

RISC-V Pros And Cons


Simpler, faster, lower-power hardware with a free, open, simple instruction set architecture? While it sounds too good to be true, efforts are underway to do just that with RISC-V, the instruction-set architecture (ISA) developed by UC Berkeley engineers and now administered by a foundation. It has been known for some time that with [getkc id="74" comment="Moore's Law"] not offering the same... » read more

The Week In Review: Design


Tools Synopsys debuted a tool to replay RTL simulation data on a gate-level netlist for power analysis the company says is accurate within 5% of signoff. The tool, PowerReplay, is design to be used in combination with PrimeTime PX gate-level power analysis for earlier and faster generation of gate-level switching data. IP ClioSoft launched a design reuse ecosystem for searching and com... » read more

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