Blog Review: Jan. 16


Mentor's Harry Foster takes a look at how quickly FPGAs are adopting recent verification techniques, with formal gaining at a rapid pace. Cadence's Paul McLellan checks out the details of two new RISC-V based cores: Western Digital's open source SweRV and Esperanto's Maxion. Synopsys' Taylor Armerding digs into a recent cybersecurity report from the U.S. government and finds a troubling n... » read more

Chip Industry In Rapid Transition


Wally Rhines, CEO Emeritus at Mentor, a Siemens Business, sat down with Semiconductor Engineering to talk about global economics, AI, the growing emphasis on customization, and the impact of security and higher abstraction levels. What follows are excerpts of that conversation. SE: Where do you see the biggest changes happening across the chip industry? Rhines: 2018 was a hot year for fab... » read more

December Startup Funding: Big Rounds As 2018 Ends


During the month of December, 16 startups had private funding rounds of $100 million and up, with half of them in the mobility area. Those 16 rounds totaled $3.2 billion as the year concluded. Before the holidays, the SoftBank Vision Fund invested $500 million in Cambridge Mobile Telematics, provider of the DriveWell platform used by insurers, vehicle fleets, wireless carriers, and others to... » read more

Top Stories For 2018


Each year, I look back to see what articles people like to read. The first thing that has amazed me each year at Semiconductor Engineering is that what should be a strong bias towards articles published early in the year never seems to play out. The same is true this year. More than half of the top articles were published after July. The second thing that remains constant is that people love... » read more

Fundamental Shifts In 2018


What surprised the industry in 2018?  While business has been strong, markets are changing, product categories are shifting and clouds are forming on the horizon. As 2018 comes to a close, most companies are pretty happy with the way everything turned out. Business has been booming, new product categories developing, and profits are meeting or beating market expectations. "2018 was indeed a... » read more

Beyond The RISC-V ISA


For chip architects and designers today, “the ISA” in RISC-V is a small consideration. The concern isn’t even choosing “the core.” Designers today are faced by a “whole system” problem—a problem of systemic complexity. That fact is implicit in the picture that I show people to explain the UltraSoC embedded analytics architecture. It shows a block-level representation of an So... » read more

More Than A Core


Gajinder Pandesar, CTO of UltraSoC, talks with Semiconductor Engineering about why heterogeneous design is changing the starting point for chip design, and why integration is now the real challenge rather than the processor core. https://youtu.be/y0rzopp5HDI » read more

Open-Source RISC-V Hardware And Security


Semiconductor Engineering sat down with Helena Handschuh, a Rambus fellow; Richard Newell, senior principal product architect at Microsemi, a Microchip Company; and Joseph Kiniry, principal scientist at Galois. What follows are excerpts of that conversation. (L-R) Joseph Kiniry, Helena Handschuh and Richard Newell. SE: Is open-source hardware more secure, or does it just open up vulnera... » read more

Week In Review: Design, Low Power


RISC-V Western Digital announced big plans for RISC-V with a new open source RISC-V core, an open standard initiative for cache coherent memory over a network, and an open source RISC-V instruction set simulator. The SweRV Core features a 2-way superscalar design with a 32-bit, 9 stage pipeline core. It has clock speeds of up to 1.8Ghz on a 28mm CMOS process technology and will be used in vari... » read more

Week In Review: Design, Low Power


Tools & IP UltraSoC debuted functional safety-focused Lockstep Monitor, a set of configurable IP blocks that are protocol aware and can be used to cross-check outputs, bus transactions, code execution, and register states between two or more redundant systems. It supports all common lockstep / redundancy architectures, including full dual-redundant lockstep, split/lock, master/checker, and... » read more

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