tag: RISC-V

HW Security: Inner Product Masking With Fault Detection Via ISE (KU Leuven, NUS, Rambus)
By Technical Paper Link - 09 Dec, 2025 - Comments: 0

A new technical paper titled "Extending and Accelerating Inner Product Masking with Fault Detection via Instruction Set Extension" was published by researchers at KU Leuven, National University of Singapore, and Rambus. Abstract  "Inner product masking is a well-studied masking countermeasure against side-channel attacks. IPM-FD further extends the IPM scheme with fault detection capabil... » read more

Roadmap for Open-Source Chiplet-Based RISC-V Systems For HPC and AI (ETH Zurich, Univ. of Bologna)
By Technical Paper Link - 25 Nov, 2025 - Comments: 0

A new technical paper titled "Toward Open-Source Chiplets for HPC and AI: Occamy and Beyond" was published by researchers at ETH Zurich and University of Bologna. Abstract: "We present a roadmap for open-source chiplet-based RISC-V systems targeting high-performance computing and artificial intelligence, aiming to close the performance gap to proprietary designs. Starting with Occamy, the f... » read more

Shaping The Future Of AI Processors: A Tech Threads Conversation With Jim Keller
By Nandan Nayampally - 25 Nov, 2025 - Comments: 0

I had the pleasure of hosting renowned computer architect and Tenstorrent CEO Jim Keller, on the latest episode of Baya Systems’ Tech Threads podcast. If you haven’t already, listen to get his insights on the need for “open” intelligence architectures and what would be needed to drive the semiconductor industry forward. What is an “open” intelligent architecture and ecosystem? As... » read more

Multi-Core Architecture Optimized For Time-Predictable Neural Network Inference (FZI, KIT)
By Technical Paper Link - 21 Nov, 2025 - Comments: 0

A new technical paper titled "MultiVic: A Time-Predictable RISC-V Multi-Core Processor Optimized for Neural Network Inference" was published by researchers at FZI Research Center for Information Technology and Karlsruhe Institute for Information Technology (KIT). Abstract: "Real-time systems, particularly those used in domains like automated driving, are increasingly adopting neural network... » read more

Opportunities And Challenges With Open-Source Hardware In System Development
By Roland Jancke - 13 Nov, 2025 - Comments: 0

For many years now, there has been a trend toward open source in the field of system development. It can be seen in software libraries for the product itself as well as in development tools. A clear motivation for open source lies in the fact that not charging license fees makes a product more attractive on the market. It may also enable further development of the software component, dependi... » read more

Developing RISC-V Compute Subsystems
By Baya Systems - 29 Oct, 2025 - Comments: 0

As demand grows for scalable, efficient, and customized compute, more companies are turning to RISC-V as the preferred architecture for high-performance computing. Tenstorrent and Baya Systems have designed a compute subsystem combining IP from both companies designed to enable AI and HPC use cases. The solution leverages Tenstorrent’s Ascalon processor and Baya’s advanced interconnect tech... » read more

Microarchitectural Defense Strategy Against EM Side-Channel Attacks (Northeastern Univ., Binghamton Univ.)
By Technical Paper Link - 20 Oct, 2025 - Comments: 0

A new technical paper titled "ShuffleV: A Microarchitectural Defense Strategy against Electromagnetic Side-Channel Attacks in Microprocessors" was published by researchers at Northeastern University and Binghamton University. Abstract "The run-time electromagnetic (EM) emanation of microprocessors presents a side-channel that leaks the confidentiality of the applications running on them. Ma... » read more

HW/SW Co-Design to Retarget the Compiler For RISC-V Custom Instructions (Tampere Univ.)
By Technical Paper Link - 16 Sep, 2025 - Comments: 0

A new technical paper titled "Automatically Retargeting Hardware and Code Generation for RISC-V Custom Instructions" was published by researchers at Tampere University. Abstract "Custom instruction (CI) set extensions are beneficial for increasing performance and energy efficiency in a set of target applications. For rapid prototyping of these types of application-specific processors, desig... » read more

Tag-Based Memory Verification System for RISC-V (Inha Univ., Intel Labs et al.)
By Technical Paper Link - 22 Jul, 2025 - Comments: 0

A new technical paper titled "Efficient Hardware-Assisted Heap Memory Safety for Embedded RISC-V Systems" was published by researchers at Inha University, Intel Labs, Electronics and Telecommunications Research Institute, and Korea National University of Education. Abstract "In recent years, memory safety issues in embedded environments have garnered significant attention, with spatial and ... » read more

HW/SW Co-Design Toolset for RISC-V (Tampere Univ.)
By Technical Paper Link - 21 Jul, 2025 - Comments: 0

A new technical paper titled "Automatically Retargeting Hardware and Code Generation for RISC-V Custom Instructions" was published by researchers at the Tampere University. Abstract "Custom instruction (CI) set extensions are beneficial for increasing performance and energy efficiency in a set of target applications. For rapid prototyping of these types of application-specific processors, d... » read more

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