Chiplets Vs. Soft IP: Different In Almost Every Way

Chiplets serve a similar function as the soft IP widely used in chips today, but the similarities end there. While both can speed time to market and enable design teams to focus limited resources where they can best be applied, the implementation, manufacturing, test, and long-term business requirements wrought by a chiplet marketplace would be very different.

Soft IP (also known as RTL IP) is a tool for designers working at the logical level, whereas chiplets provide options at the physical and system level. The considerations for each are separate and distinct, and the extra burdens that market chiplets introduce may impact whether such an approach is even viable.

“At a conceptual level, chiplets can be viewed as a new form of semiconductor IP,” said Paul Karazuba, vice president of marketing at Expedera. “However, when a true chiplet marketplace emerges, I believe it will not closely resemble today’s IP licensing ecosystem. The analogy between chiplets and soft IP breaks down in ways that span design integration, interface standards, verification, economics, and even trust. Chiplets shift the integration challenge from the logical domain of design to the physical and system level.”

Chiplets may be custom or purchased off-the-shelf. “There are two camps,” explained Lang Lin, principal product manager at Ansys (now part of Synopsys). “One uses chiplets of their own design. The other camp wants to buy everything outside and then assemble maybe an Intel chiplet with a TSMC chiplet and one from GlobalFoundries, then merge them together.”

Market chiplets would accompany custom ones. “In this new chiplet world, many — but not all — IP blocks will become off-the-shelf chiplets,” said Steve Roddy, chief marketing officer of Quadric. “These would include CPU clusters, GPU clusters, and NPU AI subsystems in mix-and-match sizes selected by the system company, plus I/O chiplets and perhaps one slice of the system OEM’s own value-add logic.”

Understanding how a chiplet market would be different from an IP market is critical to the success of any future chiplet market. “The end goal is to get chiplets to a point where they can be used like IP,” said Mayank Bhatnagar, product marketing director for die-to-die interface IP at Cadence.

But is that a realistic outcome?

Soft IP is for chip designers
Soft IP consists of pre-designed portions of a design, typically in RTL form. Some may be delivered pre-laid out in a physical file format. They may be encrypted to protect the design from being copied. Some companies may optimize their IP design for a specific process node, yielding what Arm calls “droplets,” but the deliverable is still soft IP.

Soft IP has also bulked up over the years. “If you remember the days of controller-plus-PHY, customers were mixing and matching [controller and PHY IP blocks],” said Mick Posner, senior product marketing group director at Cadence. “That stage is over. Most customers now want a subsystem of packaged IP.”

In addition to the design contents, other deliverables enable verification of both the IP in isolation (as a quality check) and the entire design once the IP has been integrated.

Soft IP vendors often design a large super-design that will cover many use cases. Customers then configure the IP with the desired characteristics, and, importantly, the synthesis tools (in the case of RTL IP) will eliminate any logic that’s unnecessary for the chosen configuration.

“When you get soft IP, you decide, ‘I want these features, but other features are no longer required,’” explained Bhatnagar. “It’s soft, so the design tools are able to blow away all the unrequired features, and you no longer have to pay the area and power penalty.”

One can even request more substantial custom changes from a soft-IP provider. “With chiplets the entire functionality is fixed, whereas with IP it is often possible to request modifications from the IP provider,” said Andy Heinig, department head of efficient electronics at Fraunhofer IIS’ Engineering of Adaptive Systems Division.

Chiplets bring a different set of requirements
At a very high level, soft IP and chiplets involve make/buy decisions. Beyond that, the considerations are very different.

“How do you manage boot?” asked Posner. “How do you manage debug? How do you manage security and authentication?”

The biggest differentiator is the ability to customize functions. “IP is very configurable,” said Eddie Ramirez, vice president of marketing for Arm’s Infrastructure Business. “Even with a compute subsystem design, you can change the core counts. You can reconfigure the dimensions.”

With chiplets, the contents are cast in silicon. If a chiplet contains an unnecessary function, it may remain unused, but it will still occupy area on the silicon and therefore add to the cost. In some cases, that cost may be tolerable.

“I believe area probably becomes less important, but power becomes very important,” said Bhatnagar. “You can still save on power by doing active clock gating. Or you can have header switches and completely cut off that circuit and save leakage power. It might be beneficial to leave the features in and make them customizable.”

Other options may have a large impact on die size. For example, it would be challenging to include both 32-bit and 64-bit interface options because choosing the 32-bit option would leave 32 bits unused, including wasted bus area and pins.

“A customer asked us for a PCIe Gen6 chip,” said Posner. “And then they also said, ‘That’s for our high-end networking product. But we want to be able to address our mid- and low-ends, so we need a ×8 and a ×4.’ The ×16 supports the ×8 or ×4, but the die size difference between a ×4 or ×8 and ×16 is quite significant. The ×4 area was less than half the size of the ×16, if you look at beachfront density.”

It’s possible to add some configuration using e-fuses to make the changes durable, or even by allowing boot-up configuration based on register values. But the configuration circuits will take some area, and any unused functions will remain.

All in the families
One can also create a family of chiplets, each of which contains different options that result in less wasted space, but each of those requires a mask set, dramatically impacting cost in a way that soft IP doesn’t.

“Maybe I have this awesome chiplet that can go in both a data center and an automotive design,” said Bhatnagar. “But for automotive, with the required heat dissipation, I am making a different version of it.”

Cadence is addressing this not by providing chiplets outright, which would compete with its customers, but with a reference foundation based on Arm’s CSA. The heavy design work has mostly been done, but the design remains soft pending final feature configuration. The customer must then proceed with the standard chip-design backend to harden the configured design.

“In the physical AI space (automotive, robotics, drones, aerospace, and defense), we are building a complete reference platform,” said Posner. “They all have very similar application use cases. They need a processing CPU, an AI engine, and a system interface with PCIe and memories. But automotive ADAS needs a lot more AI processing power. A reference platform that offered only a four-core NPU isn’t going to cut it for automotive. But when you look at drones and robotics, that’s usually enough.”

Arm’s CSA can be employed for chiplets not using the Arm CPU architecture. “Arm is contributing CSA to the OCP,” said Posner. “We believe that is going to help the market converge.”

Who leads the boot?
Meanwhile, each chiplet must boot up. But if each does so independently, resources may not be used efficiently, such as with multiple independent firmware files. What’s more likely is that one chiplet will get lead-chiplet status.

“You can always design your boot architecture in a way that you can do things in parallel,” said Pratyush Kamal, director of central engineering solutions at Siemens EDA. “But at the system level, you still have a single entity [the lead chiplet] triggering the action.”

Still, with too many chiplets, having only one lead chiplet may slow the boot process unacceptably, making a hierarchical approach necessary. “With a 1,000-chiplet system, you’ll have to go through an H3 kind of boot sequence, where things trigger in parallel in a second or third or fourth [hierarchy] layer,” Kamal said.

In this scenario, a chiplet’s data sheet should say whether the chiplet can act as a boot-up lead. It also may be possible to make every chiplet lead-capable, with a setting that determines whether it acts as one in each design. “Standalone boot doesn’t add much [area] overhead,” said Posner. “You require a connection to a boot ROM, which could be stubbed out.”

A lead boot-up chiplet might not only coordinate the booting of other chiplets but also the power-up sequence for those chiplets.

Shape shifting
Chiplets have a rectangular shape. Absent any standards on allowable shapes, this can make it much more difficult to be sure that a set of chiplets will fit together in a way that keeps the leads between chiplets short.

“If your package has a dimension of, say, 2mm by 3mm available for a chiplet, but in the marketplace the chiplet you get is 2.5mm by 2.5mm, the area is roughly the same, but one dimension now exceeds the space you have,” said Bhatnagar.

This can cause problems. “Sometimes you need a die that has specific x and y dimensions,” said Arm’s Ramirez. “With IP, you can change it. With chiplets, you can’t.”

Fig. 1: Different physical chiplet assemblies. The large chiplet has two interfaces. The top part shows a configuration that works well. The bottom shows a configuration that makes some of the interface lines too long and with different lengths, contributing to skew. Source: Bryon Moyer/Semiconductor Engineering

The darker chiplet in Figure 1 has two interfaces, one on the left side and one on the top toward the left. The top portion of the drawing shows a configuration where this arrangement works. A chiplet to the left and one above allow for short connections.

The bottom example is a problem, however, since the top interface must make an angle to get to the chiplet on the left. These connections are longer than desired and are of unequal length, increasing signal skew. Some die-to-die (D2D) interconnect schemes allow for some de-skewing, but what’s shown above may be too much.

Rob Kruger, product management director at Synopsys, gave some examples of other potential shape challenges, some of which must be documented in a chiplet data sheet. “If you use UCIe-Advanced because of the signal routing density, you get only two millimeters [of trace length],” he said. The second example above wouldn’t work for that. “If you have a PCIe interface with inductors on top, you might have a keep-out area above that.”

It’s possible for a chiplet designer to create two packages, one as shown and another with a different shape that mates better in the lower example. But that would require a separate layout and mask set, which would increase the cost.

Meanwhile, if the interfaces on two chiplets have lanes ordered in opposing directions, then the interfaces don’t truly match up even though they’re physically aligned. This issue can be solved with a D2D interface that allows lane reversal.

Fig. 2. Interfaces that match physically but have lines numbered in the opposite direction. Some D2D interconnects allow for lane reversal, which would solve the issue. Source: Bryon Moyer/Semiconductor Engineering

The packaging style also matters, as it affects pinout and power. “There is work to be done in advanced packaging so that a single die could be used across multiple packaging technologies,” said Posner. “If you design something for advanced packaging — interposer-based — then there’s a compatibility issue. If you look at CoWoS versus EMIB versus Samsung Cube technology, their power delivery schemes are not the same.”

Everyone must agree on security
Security is another aspect that presents far more of a challenge than would be the case with soft IP. “While IP-level security focuses on license protections and IP security verification, chiplets greatly grow the attack surfaces,” said Expedera’s Karazuba. “Die-to-die interfaces, shared power planes, and thermal channels all present potential side-channel or tampering vectors. A multi-chiplet system will require trusted supply-chain verification, hardware attestation, and certification frameworks, especially in security-critical applications like defense and automotive.”

And since a collection of chiplets is intended to work together as if it were a single chip, how will security be partitioned? Replicating it on every chiplet will consume more silicon than necessary. Resources such as the root of trust (RoT) must be coordinated at the package or system level. “Your RoT could be on the chiplet you’re buying, or it could be something that you have in your own system,” said Kruger.

To account for this, one chiplet could be designated as containing the root of trust (RoT), with the other chiplets looking to that one for tasks such as authentication and encryption. As with lead boot-up status, this capability is something that would need to be declared on a data sheet.

Soft IP, because it’s integrated into a design, is harder — perhaps just short of impossible — to isolate. Doing so would mean delaminating the chip, which is possible but destructive and expensive.

Breaking down a package to expose internal chiplets is also a difficult process, but far less so than taking a die apart. So, for example, the D2D interfaces can be exposed and tapped if they run on top of a substrate or interposer.

Additionally, power planes may or may not be shared. If not, then it may be possible to isolate the power for each chiplet, providing side-channel access. Heat dissipation also can leak secrets, and separate chiplets will provide separate thermal channels that can be analyzed.

Manufacturing requires support
Chiplets, unlike soft IP, exist in isolation. A company acquiring chiplets receives a pre-built piece of silicon. That company will need the continued availability of that chiplet for the expected lifetime of a design. That ongoing supply must be attested to ensure that no counterfeit chiplets are inadvertently being purchased.

Testing adds other challenges. Soft IP typically is not tested in isolation once it’s integrated. Instead, automatic test-pattern generation (ATPG) tools analyze the complete chip design and generate an efficient set of test vectors.

A chiplet vendor rather than a chiplet integrator will handle chiplet testing in isolation, although the test coverage provided is likely to be information an integrator would request to ensure good system-test yields. “You’re going to wonder, ‘What’s their DFT (design-for-test) like? Are they giving it enough coverage?’” said Kruger.

But the integrator also needs test vectors to work into the overall system-test flow. ATPG may generate those vectors, but it’s the IP provider creating them, not the integrator.

Because test vectors may provide insights into a chiplet’s inner workings, it may be desirable to encrypt the vectors. Doing so would necessitate collaboration between ATPG vendors and test equipment vendors to ensure that the testers could decrypt the vectors for use.

Likely to see more BiST
Built-in self-test (BiST) can help address a chiplet’s lack of transparency, although its effectiveness must be demonstrable. “The chiplet vendor has a mechanism to check their chiplet without having to integrate it at a flat level in your SoC,” said Bhatnagar.

The sequence of tests is also important with multiple chiplets. Each die being tested creates heat. “You may not even be able to test a three-die stack in tandem because of thermal or power limitations,” noted Kamal. “You have to plan your test scheduling.”

Given that the chiplets are accessible only through the package pins, a uniform debug strategy is necessary. With soft IP, it’s possible to alter the logic to ensure consistency within a chip. No such alterations are possible with chiplets.

Chiplets also imply a supply chain that soft IP lacks. “Soft IP is distributed digitally, with its recurring costs essentially zero once released,” explained Karazuba. “Chiplet supply chains are wildly different and most closely resemble that of traditional chips. They are tied to process nodes and foundries, limiting portability and increasing dependency on vendors.”

“The key challenge is the supply of silicon,” said Benjamin Prautsch, group manager, advanced mixed-signal automation at Fraunhofer IIS/EAS. “The supply must be guaranteed, as multiple vendors will likely be involved. A key difference will be how the supply information will reach the design team when selecting chiplets for their product.”

Designing for the physical level
There are other important differences, as well. “Traditional IP blocks are integrated at the logical level,” said Karazuba. “In contrast, chiplets are integrated physically at the package level. Their interconnects exist as physical connections, not as bus interfaces. As a result, designers must manage die-to-die signaling, power integrity, and package routing alongside chip design.”

Each chiplet generates heat that must escape the package without disturbing other chiplets (especially HBM). That means the integrator needs thermal and other physical models to verify that the thermal characteristics of the assembled package will pass muster.

“Chiplets, like chips, require robust models, including behavioral, power, thermal, and interface models for signal and power integrity that are above and beyond what is required for soft IP,” said Steven Woo, fellow and distinguished inventor at Rambus.

Physical stresses are also a consideration. Large interposers, for example, are more prone to warping than small ones. Analysis must ensure sufficient planarity to maintain the necessary reliability in the field.

Chiplet vendors will therefore need to deliver multi-physics models so that integrators can take any necessary steps to mitigate thermal and other physical issues. The multi-physics verification tools are unlike those employed in chip design. Instead, they tend to resemble system-level tools and may be unfamiliar to chip designers.

Other considerations include:

• Ensuring that all chiplets agree on the protocols through which they will interact. Both sides of an interface must agree all the way up the protocol stack.
• Address maps must match across chiplets using them.
• A control mechanism must be agreed upon.
• Chiplets must agree on how interrupts are to be handled.

Visibility is also more limited with chiplets. “Soft IP is typically delivered with at least partial transparency, such as timing constraints, synthesizable RTL, or models that allow detailed optimization,” said Karazuba. “Chiplets, however, are ‘black boxes.’ Designers receive abstracted timing, power, and thermal models, but no visibility into internal logic.”

The questions that need to be answered are different, too. “If you deliver an IP block, you’re going to want to have something like Spyglass models and some test bench,” said Kruger. “You don’t have to worry about that when you buy a chiplet off the shelf, since all that’s done for you. But now you’re worrying about a different set of questions. How does it fit my package? How does it thermally fit? And are there any hot spots because of the high signal speed in a narrow area?”

3D makes things worse
If chiplets are to be stacked atop each other, additional requirements emerge. “The biggest constraint you have is the I/O and the power supply footprint that you have available,” said Kamal.

Test access is more challenging since one no longer has direct access to each individual chiplet. The stack must be tested as a whole. That requires ensuring that each die can deliver vectors to chiplets above it. Alternatively, greater use of BiST would reduce the need for testing under the control of an external system.

A subtler issue comes from the fact that most standard chips have, in addition to mission-critical high-speed interfaces, numerous slow interfaces typically used for configuration, testing, or debugging. Examples are SPI, I²C, and JTAG. If each die in the stack requires them, it boosts the number of signals that must make their way out of the bottom die.

Such signals often provide out-of-band capabilities that don’t impact the main interfaces. But it may be necessary to combine such signals and either place them in-band or build a separate combined slow interface that can serve all the chiplets in the stack to minimize the I/O footprint.

Chiplet IP is a heavier lift than soft IP
Many of the above considerations can be addressed given time and effort. But some are particularly thorny. It’s hard to imagine how chiplet shapes can be addressed short of providing multiple versions of a chiplet. Configurability is an important aspect of soft IP, and today it’s unclear what types of functions are so fixed that they merit a chiplet with little or no adaptability.

Even if the chiplet marketplace materializes, soft IP will still have a big role. “An AI company such as Quadric might have a ready-made scalable roster of chiplets ready off-the-shelf, but also still sell IP to companies wanting to build high-volume monolithic ICs,” said Roddy.

Many designs will include a mix of chiplets and soft IP. “While chiplets may embody the next evolution of IP reuse, they will not in any way replace soft IP,” said Karazuba. “Chip architects should not treat chiplets as interchangeable RTL modules. Instead, they should treat them more as system-level building blocks with distinct physical, economic, and security implications.”

Nevertheless, if the chiplet market materializes, chiplet users will operate very differently from soft-IP users.

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