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Efficient Ohmic contacts and built-in atomic sublayer protection in MoSi2N4 and WSi2N4 monolayers


Abstract "Metal contacts to two-dimensional (2D) semiconductors are often plagued by the strong Fermi level pinning (FLP) effect which reduces the tunability of the Schottky barrier height (SBH) and degrades the performance of 2D semiconductor devices. Here, we show that MoSi2N4 and WSi2N4 monolayers—an emerging 2D semiconductor family with exceptional physical properties—exhibit stron... » read more

Power/Performance Bits: Dec. 6


Tunable 2D semiconductors Researchers from the Singapore University of Technology and Design (SUTD), Hengyang Normal University, Nanjing University, National University of Singapore, and Zhejiang University identified a family of 2D semiconductors that could have lower resistance and enable further scaling. “Due to the quantum tunnelling effect, shrinking a silicon-based transistor too sm... » read more

Power/Performance Bits: Nov. 2


GaN CMOS ICs Researchers from the Hong Kong University of Science and Technology (HKUST) are working to increase the functionality available to wide bandgap gallium nitride (GaN) electronics. GaN is frequently used in power electronics, such as power converters and supplies. However, GaN CMOS technology has been hampered by the difficulties in implementing p-channel transistors and integrat... » read more

Power/Performance Bits: Oct. 5


Modeling resistive-switching memory Researchers from Singapore University of Technology and Design (SUTD) and Chang Gung University developed a new toolkit for modeling current in resistive-switching memory devices. The team said that traditional physical-based models need to consider complex behaviors to model current in resistive memory, and there's a risk of permanent device damage due t... » read more

Modeling electrical conduction in resistive-switching memory through machine learning


Published in AIP Advances on July 13, 2021. Read the full paper (open access). Abstract Traditional physical-based models have generally been used to model the resistive-switching behavior of resistive-switching memory (RSM). Recently, vacancy-based conduction-filament (CF) growth models have been used to model device characteristics of a wide range of RSM devices. However, few have focused o... » read more

Power/Performance Bits: Nov. 19


Quantum communications chip Researchers at Nanyang Technological University, Australian National University, A∗STAR, University of Science and Technology of China, Singapore University of Technology and Design, Sun Yat-sen University, Beijing University of Posts and Telecommunications, and National University of Singapore built an integrated silicon photonic chip capable of performing quantu... » read more

Manufacturing Bits: Oct. 1


3D balloon printing Using an elastomeric or stretchy balloon, the University of Houston and the University of Colorado have developed a new 3D printing method as a means to develop three-dimensional curvy electronic products. The technology involves the field of 3D printing, sometimes known as additive manufacturing (AM). In 3D printing, the goal is to develop parts layer-by-layer using mat... » read more

Manufacturing Bits: Aug. 27


Holographic lithography Switzerland’s Nanotech SWHL GmbH has come out of stealth mode and disclosed its initial technology—a holographic lithography system. Founded in 2015, Nanotech SWHL has developed a sub-wavelength holographic lithography system that generates and prints 3D images on surfaces with one mask at one exposure. Still in R&D, the system is initially targeted for advanced ... » read more

System Bits: July 10


Light waves run on silicon-based chips Researchers at the University of Sydney’s Nano Institute and Singapore University of Technology and Design collaborated on manipulating light waves on silicon-based microchips to keep coherent data as it travels thousands of miles on fiber-optic cables. Such waves—whether a tsunami or a photonic packet of information—are known as solitons. The... » read more

Manufacturing Bits: June 10


Predicting warpage in packages At the recent IEEE Electronic Components and Technology Conference (ECTC) in Las Vegas, there were several papers on ways to predict variation and warpage in IC packages. Advanced packages are prone to unwanted warpage during the process flow. The warpage challenges escalate as the packages become thinner. Warpage in turn can impact yields in IC packages. ... » read more

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