Chip Industry’s Technical Paper Roundup: Mar. 21

Scalable spintronics manufacturing; cross-layer techniques; 3DIC metal bonding; memristor-based ANNs; shift register-in-memory; cache coherence; graphite film as a EUV pellicle; virtual prototyping for packaging; cross-bar based CIM for neural networks; AMS circuit learning.


New technical papers recently added to Semiconductor Engineering’s library:

Technical Paper Research Organizations
Scalable Spintronics Manufacturing Process
Sputtered L10-FePd and its Synthetic Antiferromagnet on Si/SiO2 Wafers for Scalable Spintronics
University of Minnesota and NIST, with funding by DARPA and others
MetaSys: A Practical Open-Source Metadata Management System to Implement and Evaluate Cross-Layer Optimizations University of Toronto, ETH Zurich, and Carnegie Mellon University
(Best Paper winner)
Toward Single-Cell Multiple-Strategy Processing Shift Register Powered by
Phase-Change Memory Materials
Singapore University of Technology and Design and University of Cambridge
ReMeCo: Reliable Memristor-Based in-Memory Neuromorphic Computation Eindhoven University of Technology, University of Tehran, and USC
Room-Temperature Direct Cu Semi-Additive Plating (SAP) Bonding for Chip-on-Wafer 3D Heterogenous Integration With μLED Tohoku University (Japan)
TAG: Learning Circuit Spatial Embedding From Layouts UT Austin and NVIDIA
WARDen: Specializing Cache Coherence for High-Level Parallel Languages Northwestern University and Carnegie Mellon University
Graphite Pellicle: Physical Shield for Next-Generation EUV Lithography Technology University of Ottawa, Sungkyunkwan University, and Hanbat National University
Design Optimization by Virtual Prototyping Using Numerical Simulation to Ensure Thermomechanical Reliability in the Assembly and Interconnection of Electronic Assemblies Fraunhofer ENAS
Compute in-Memory with Non-Volatile Elements for Neural Networks: A Review from a Co-Design Perspective Argonne National Lab, Purdue University, and Indian Institute of Technology Madras

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