Reducing The Cost of Cache Coherence By Integrating HW Coherence Protocol Directly With The Programming Language


A new technical paper titled “WARDen: Specializing Cache Coherence for High-Level Parallel Languages” was published by researchers at Northwestern University and Carnegie Mellon University.


“High-level parallel languages (HLPLs) make it easier to write correct parallel programs. Disciplined memory usage in these languages enables new optimizations for hardware bottlenecks, such as cache coherence. In this work, we show how to reduce the costs of cache coherence by integrating the hardware coherence protocol directly with the programming language; no programmer effort or static analysis is required.

We identify a new low-level memory property, WARD (WAW Apathy and RAW Dependence-freedom), by construction in HLPL programs. We design a new coherence protocol, WARDen, to selectively disable coherence using WARD.

We evaluate WARDen with a widely-used HLPL benchmark suite on both current and future x64 machine structures. WARDen both accelerates the benchmarks (by an average of 1.46x) and reduces energy (by 23%) by eliminating unnecessary data movement and coherency messages.”

Find the technical paper here. Published February 2023.

Wilkins, Michael, Sam Westrick, Vijay Kandiah, Alex Bernat, Brian Suchy, Enrico Armenio Deiana, Simone Campanoni, Umut A. Acar, Peter Dinda, and Nikos Hardavellas. “WARDen: Specializing Cache Coherence for High-Level Parallel Languages.” (2023).

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