Why Your NoC Verification Strategy Must Consider Using Formal


By Ashish Darbari and Bing Xue It’d be inconceivable these days to design a modern high-performance SoC without a network-on-chip (NoC) fabric. AI hyperscalers are inherently multi-threaded and rely on using hundreds of processing elements (PEs). Crossbar-based fabric would just not scale. What also changes with the adoption of the NoC is how to handle coherency between PEs. ACE is no long... » read more

NoC Coherency Challenges Balloon With AI SoCs And Chiplets


Key Takeaways Data movement, congestion, and energy efficiency are key determiners of whether compute is usable. Different processors bring various coherency challenges. For example, a cache-coherent NoC for CPUs is expensive and harder to verify than an I/O-coherent NoC for an accelerator. Designers need to balance top-down performance with bottom-up physical engineering to effect... » read more

Balancing Memory And Coherence: Navigating Modern Chip Architectures


In the intricate world of modern chip architectures, the "memory wall" – the limitations posed by external DRAM accesses on performance and power consumption growing slower than the ability to compute data – has emerged as a pivotal challenge. Architects must strike a delicate balance between leveraging local data reuse and managing external memory accesses. While caches are critical for op... » read more

RISC-V Driving New Verification Concepts


Semiconductor Engineering sat down to discuss gaps in tools and why new methodologies are needed for RISC-V processors, with Pete Hardee, group director for product management at Cadence; Mike Eftimakis, vice president for strategy and ecosystem at Codasip; Simon Davidmann, founder and CEO of Imperas Software; Sven Beyer, program manager for processor verification at Siemens EDA; Kiran Vittal, ... » read more

Reducing The Cost of Cache Coherence By Integrating HW Coherence Protocol Directly With The Programming Language


A new technical paper titled "WARDen: Specializing Cache Coherence for High-Level Parallel Languages" was published by researchers at Northwestern University and Carnegie Mellon University. Abstract: "High-level parallel languages (HLPLs) make it easier to write correct parallel programs. Disciplined memory usage in these languages enables new optimizations for hardware bottlenecks, such ... » read more

The New CXL Standard


Gary Ruggles, senior staff product marketing manager at Synopsys, digs into the new Compute Express Link standard, why it’s important for high bandwidth in AI/ML applications, where it came from, and how to apply it in current and future designs. » read more

Impacts Of Reliability On Power And Performance


Making sure a complex system performs as planned, and providing proper access to memories, requires a series of delicate tradeoffs that often were ignored in the past. But with performance improvements increasingly tied to architectures and microarchitectures, rather than just scaling to the next node, approaches such as determinism and different kinds of caching increasingly are becoming criti... » read more

Coherency: The New Normal In SoCs


We are not far from devices each handling 100 teraflops of compute, billions of pixels of display, hundreds of gigabits of connectivity, and terabytes of storage. Compared with current state-of-the-art mobile SoCs, these are increases of one or two orders of magnitude — at similar or preferably lower power consumption. SoC design is changing to meet this challenge. Multicore architecture i... » read more

Adapt Or Perish: A Unified Theory Of Coherency


Evolution is a natural process and more importantly a relatively slow process that has eventually got us here, capable of perceiving, analyzing, and handling complex tasks. As our environment, society, and surroundings became more complex we learned how to adapt at a brisk and instantaneous manner, in this melting pot of a heterogeneous world. The evidence can be seen in all ages, from the poli... » read more

The Mightier Microcontroller


Microcontrollers are becoming more complex, more powerful, and significantly more useful, but those improvements come with strings attached. While it's relatively straightforward to develop multi-core microcontroller (MCU) hardware with advanced power management features, it's much more difficult to write software for these chips because memory is limited. CPUs can use on-chip memory such as... » read more

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