Chip Industry Week In Review


The U.S. Department of Commerce and Amkor Technology signed a deal to provide up to $400 million in funding, under the CHIPS and Science Act, to build a previously announced end-to-end advanced packaging plant. The combined funding is expected to total about $2 billion. The new facility will add some 2,000 jobs in Peoria, Arizona. The SK hynix Board approved its Yongin Semiconductor Cluster... » read more

Research Bits: July 22


Sub-1nm gate Researchers from Korea's Institute for Basic Science, Sungkyunkwan University, Harvard University, and Korea Advanced Institute of Science and Technology (KAIST) found a method that enables epitaxial growth of 1D metallic materials with a width of less than 1 nm, which they used as a gate electrode of a miniaturized transistor. The team controlled the crystal structure of molyb... » read more

Chip Industry Technical Paper Roundup: July 8


New technical papers recently added to Semiconductor Engineering’s library. [table id=238 /] More ReadingTechnical Paper Library home » read more

A Memory Device With MoS2 Channel For High-Density 3D NAND Flash-Based In-Memory Computing


A technical paper titled “Low-Power Charge Trap Flash Memory with MoS2 Channel for High-Density In-Memory Computing" was published by researchers at Kyungpook National University, Sungkyunkwan University, Dankook University, and Kwangwoon University. Abstract: "With the rise of on-device artificial intelligence (AI) technology, the demand for in-memory computing has surged for data-intensiv... » read more

Research Bits: Apr. 2


Stretchy, sensitive circuits Researchers from Stanford University developed skin-like, stretchable integrated circuits capable of driving a micro-LED screen with a refresh rate of 60 Hz and detecting a braille array that is more sensitive than human fingertips. The stretchable transistors are made from semiconducting carbon nanotubes sandwiched between soft elastic electronic materials. The... » read more

Technical Paper Roundup: November 21


New technical papers recently added to Semiconductor Engineering’s library: [table id=167 /] More Reading Technical Paper Library home » read more

High-Speed Sparse Scanning Kelvin Probe Force Microscopy


A technical paper titled “High-speed mapping of surface charge dynamics using sparse scanning Kelvin probe force microscopy” was published by researchers at Oak Ridge National Laboratory, (ORNL), Sungkyunkwan University, Case Western Reserve University, Flinders University, Bedford Park, and UNSW Sydney. Abstract: "Unraveling local dynamic charge processes is vital for progress in diverse... » read more

Technical Paper Roundup: November 14


New technical papers added to Semiconductor Engineering’s library this week. [table id=165 /] More Reading Technical Paper Library home » read more

Stacked Ferroelectric Memory Array Comprised Of Laterally Gated Ferroelectric Field-Effect Transistors


A technical paper titled “Laterally gated ferroelectric field effect transistor (LG-FeFET) using α-In2Se3  for stacked in-memory computing array” was published by researchers at Samsung Electronics and Sungkyunkwan University. Abstract: "In-memory computing is an attractive alternative for handling data-intensive tasks as it employs parallel processing without the need for data transfe... » read more

Applying a Floating Gate Field Effect Transistor To A Logic-in-Memory Application Circuit Design


A technical paper titled “Analysis of Logic-in-Memory Full Adder Circuit With Floating Gate Field Effect Transistor (FGFET)” was published by researchers at Konkuk University, Korea National University of Transportation, Samsung Electronics, and Sungkyunkwan University. Abstract: "The high data throughput and high energy efficiency required recently are increasingly difficult to implement... » read more

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